Well Extensions for trench devices

• US 4,808,543 A
• Filed: 05/07/1986
• Issued: 02/28/1989
• Est. Priority Date: 05/07/1986
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Mauntel, Richard W., Parrillo, Louis C., Barden, John M.
• Primary Examiner(s): Chaudhuri, Olik
• Application Number:
  US06/860,734
• Time in Patent Office: 1,028 Days
• Field of Search: 437/38, 437/47, 437/52, 437/78, 357/23.6
• US Class Current: 438/390
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/945 Trench capacitors

Abstract

A bulge well structure for trench devices in wells of a conductivity type opposite to that of the substrate where the bottom of the trench has localized, extra doping. The additional doping into the bottom of the trench prior to device formation may be implanted while the photoresist mask for the trench formation is still in place. In one embodiment of the method, the trenches and the bulge or well extension formations at their bottoms are created before isolation regions are formed. The structure and method permit increased doping only where needed and are compatible with thin epitaxial layers and sharp transition interfaces of epitaxy with substrate for optimum latchup protection. No extra masks are required and the tight packing allowed by trench technology is not altered. Protection against soft errors and junction leakage by forming DRAM trench capacitors in a well of opposite conductivity type from the substrate may be provided.

Claims

1. A method for making a semiconductor integrated circuit in a semiconductor substrate comprising the steps of:

forming at least one doped well region of one conductivity type in the face of the semiconductor substrate, the doped well region having a bottom;

forming a plurality of trenches in the doped well region using a masking pattern, each trench having a bottom; and

forming at least one impurity region of the same conductivity type as the doped well region, the impurity region located at the bottom of the trenches, and extending below the bottom of the doped well region;

comprising the steps of;

first, distributing an impurity of the same conductivity type as the doped well region solely into the bottom of the trenches using the same masking pattern used to form the trenches; and

second, driving in the impurity to form a concentration of impurity around the bottom of each of the trenches so that the resultant impurity regions expand the bottom of the doped well regions.

2. The method for making a semiconductor integrated circuit of claim 1 in which isolation regions are subsequently formed after the formation of the impurity region.

3. The method for making a semiconductor integrated circuit of claim 2 in which passive or active devices are formed within the trenches after the formation of the isolation regions.

4. The method of claim 1 in which the impurity of the same conductivity type as the doped well region is distributed by ion implantation into the bottom of the trench.

5. A method for making a semiconductor integrated circuit in a semiconductor substrate comprising the steps of:

forming at least one doped well region of a conductivity type which is the opposite conductivity type as that of the semiconductor substrate, in a face of the semiconductor substrate, the doped well region having a bottom;

forming a plurality of trenches within the doped well region substantially perpendicular to the substrate face using a masking pattern, each trench having a bottom;

forming at least one impurity region of the same conductivity type as the doped well region, the impurity region located at the bottom of the trenches, and extending below the bottom of the doped well region;

comprising the steps of;

first, distributing an impurity of the same conductivity type as the doped well region solely into the bottom of the trenches using the same masking pattern used to form the trenches; and

second, driving in the impurity to form a concentration of impurity around the bottom of each of the trenches so that the resultant impurity regions expand the bottom of the doped well regions; and

forming at least one isolation region.

6. The method of claim 5 in which the impurity of the same conductivity type as the doped well region is distributed by ion implantation into the bottom of the trench.

7. A method for making a semiconductor integrated circuit bulge well structure in a semiconductor substrate comprising the steps of:

forming an epitaxial layer of one conductivity type upon a face of the semiconductor substrate;

forming at least one doped well region of the opposite conductivity type as that of the epitaxial layer, in the epitaxial layer, the doped well region having a bottom;

forming a plurality of trenches within the doped well region substantially perpendicular to the substrate face using a masking pattern, each trench having a bottom;

forming at least one impurity region of the same conductivity type as the doped well region, the impurity region located at the bottom of the trenches, and extending below the bottom of the doped well region, comprising the steps of;

first, distributing an impurity of the same conductivity type as the doped well region solely into the bottom of the trenches using the same masking pattern used to form the trenches; and

second, driving in the impurity to form a concentration of impurity around the bottom of each of the trenches so that the resultant impurity regions expand the bottom of the doped well regions; and

forming an isolation region.

8. The method of claim 7 in which the impurity of the same conductivity type as the doped well region is distributed by ion implantation into the bottom of the trench.