Microcomputer system with watchdog timer

• US 4,809,280 A
• Filed: 12/17/1987
• Issued: 02/28/1989
• Est. Priority Date: 06/12/1984
• Status: Expired due to Fees

• Current Assignee: Omron Tateisi Electronics Co. (Omron Corporation)
• Original Assignee: Omron Tateisi Electronics Co. (Omron Corporation)
• Inventors: Shonaka, Hisashi
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Napiorkowski, Maria
• Application Number:
  US07/136,442
• Time in Patent Office: 439 Days
• Field of Search: 371/3, 371/62, 364/200 MS File, 364/900 MS File
• US Class Current: 714/55
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

A microcomputer executes a certain system program with a microprocessor according to a certain system clock. The microcomputer includes a watchdog timer circuit provided external to the microcomputer which counts a certain time interval by counting a certain timer clock which is separate from the system clock with a counter for a certain count and, upon completion of the counting, forcibly resets the microprocessor of the microcomputer. The system program of the microprocessor has a step of producing a reset output to the counter before a predetermined time only when the system action is normal. There is provided a timer circuit which counts the system clock of the microcomputer with a certain counter for a certain number of counts, counting a time interval which is slightly longer than the normal period of the timer clock of the watchdog timer circuit, and upon completion of the counting interrupts the microprocessor of the microcomputer. The system program of the microcomputer has a step in which reset output is supplied to the counter of the timer circuit in a repeated manner according to the monitoring result of the timer clock of the watchdog timer so as to respond to either the rise or the fall of the timer clock, and a step in which an abnormal output is produced to the outside in response to the interruption from the timer circuit. Thereby, the operation of the microcomputer and of the watchdog timer can be effectively checked and monitored.

Claims

1. A microcomputer system, comprising:

(a) an abnormal state display means,

(b) a microcomputer comprising;

(i) a microprocessor means, and

(ii) a system clock means for producing system clock signals,

(c) a watchdog timer circuit external to the microcomputer comprising;

(i) a timer clock, different from said system clock means, for producing timer clock signals,

(ii) a counter means for receiving and counting said timer clock signals, and upon reaching a first predetermined count indicating passage of a first time interval since reset of said watchdog timer circuit, causing forcible reset of said microprocessor means,

(d) a timer circuit means including a counter receiving and counting said system clock signals, and upon reaching a second predetermined count indicating passage of a second time interval since reset of said timer circuit means, causing one of (i) forcible resetting of said microprocessor means and (ii) activation of said abnormal state display means,

(e) said microprocessor means comprising means for;

(i) detecting, in cooperation with said timer circuit means, whether an abnormal condition exists in said watchdog timer circuit and generating an abnormal condition signal in response to a detection of an abnormal condition,

(ii) causing a reset output signal to be supplied to said counter means of said watchdog timer circuit prior to said counter means reaching said first predetermined count, unless a said abnormal condition signal has been generated,

(iii) in response to occurrence of each of said timer clock signals of said watchdog timer circuit, supplying repeated reset output signals to said counter of said timer circuit means to reset said timer circuit means to prevent its counter from reaching said second predetermined count, and

(iv) stopping supplying of said repeated reset output signal to said counter of said timer circuit means in response to detection of said abnormal condition existing in said watchdog timer circuit, said counter of said timer circuit means reaching said second predetermined count in an absence of receipt of one of said repeated reset output signals during said second time interval.

2. The microcomputer system as in claim 1, wherein said microprocessor means comprises means, responsive to an interruption in occurrence of said timer clock signals from said timer clock of said watchdog timer circuit, for providing a signal causing activation of said abnormal state display means and reset of said microprocessor means.