Sample-and-hold phase detector circuit

• US 4,810,904 A
• Filed: 06/06/1988
• Issued: 03/07/1989
• Est. Priority Date: 07/17/1985
• Status: Expired due to Term

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Crawford, James A.
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US07/205,553
• Time in Patent Office: 274 Days
• Field of Search: 307/352, 307/353, 307/319, 307/321, 307/257
• US Class Current: 327/33
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/1077 by changing characteristics of the phase or frequency detection means H03L7/1072 takes precedence
• CPC Class Codes: H03L 7/199 with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation

Abstract

A sample-and-hold phase detector (30, 80, 90, 100, 110) which includes sample-and-hold circuitry (FIG. 6) having variable efficiency. Specifically, the sample-and-hold circuitry provides a sampling pulse of variable width which is controlled to be wider during acquisition and narrower during steady-state operation. Also provided is protection circuitry to neutralize leakage of the input signal to the output of the circuit when a sample control signal is not present.

Claims

1. A sample-and-hold circuit responsive to a sample control signal for sampling an input signal provided by a signal generator, which has a characteristic resistance, during a sample interval of controllable duration, comprising:

a hold capacitor having a capacitance value selected in regard to the value of said signal generator characteristic resistance such that the RC time constant resulting therefrom is less than the duration of the selected sample interval;

sample pulse means for defining the sample interval by providing a sample pulse controllably having a first duration or a second duration which is greater than said first duration, comprising;

a step recovery diode having a depletion time dependent upon its level of bias;

bias means for providing bias current to said step recovery diode and for controlling the level of said bias current to control the duration of said sample pulse and to effect switching of said step recovery diode between on and off states in response to said sample control signal; and

pulse means responsive to the switching of said step recovery diode for generating said sample pulse of variable duration;

switching means responsive to said sample pulse of variable duration for providing a low impedance coupling of said input signal to said hold capacitor during the presence of said sample pulse, and for providing a high impedance coupling of the input signal to said hold capacitor in the absence of said sample pulse.

2. The sample-and-hold circuit of claim 1 wherein said pulse means includes a transformer.

3. A sample-and-hold circuit responsive to a sample control signal for sampling an input signal provided by a signal generator, which has a characteristic resistance, during a sample interval of controllable duration, comprising:

a hold capaciator having a capacitance value selected in regard to the value of said signal generator characteristic resistance such that the RC time constant resulting therefrom is less than the duration of the selected sample interval;

sample pulse means for defining the sample interval by providing a sample pulse controllably having a first duration or a second duration which is greater than said first duration;

switching means responsive to said sample pulse of variable duration for providing a low impedance coupling of said input signal to said hold capacitor during the presence of said sample pulse, and for providing a high impedance coupling of the input signal to said hold capacitor in the absence of said sample pulse; and

neutralizing means coupled to said hold capacitor and responsive to said input signal for neutralizing leakage current perturbations on said hold capacitor.

4. The sample-and-hold circuit of claim 3 wherein said neutralizing means provides a neutralizing signal to said hold capacitor to cancel the effect of said input signal when said switching means is providing said high impedance coupling.

5. The sample-and-hold circuit of claim 4 wherein said neutralizing means includes a phase inverter responsive to said input signal.

6. The sample-and-hold circuit of claim 5 wherein said phase inverter comprises an FET amplifier.

7. A sample-and-hold circuit for sampling an input signal comprising:

sample pulse means responsive to a sample control signal for providing a sampling pulse;

pulse width control means for selectively controlling the width of said sampling pulse, comprising;

a diode having a stored charge depletion time dependent upon bias level; and

bias means for providing bias current to said diode and for controlling the level of said bias current to control the width of said sample pulse;

wherein said sample pulse means comprises pulse means for selectively depleting the stored charge of said diode in response to the sample control signal;

switching means responsive to the input signal and said sampling pulse for providing a sampled signal as a function of the input voltage during the presence of said sampling pulse; and

storage means for storing said sampled signal.

8. The sample-and-hold circuit of claim 7 wherein said bias means comprises a controlled current source for selectively varying the forward bias current through said diode.