FET switch circuit having small insertion loss and exhibiting stable operation
First Claim
Patent Images
1. A switch circuit comprising:
- a first input/output terminal;
a second input/output terminal;
a third input/output terminal;
a fixed potential terminal;
a first field effect transistor inserted in series between said first input/output terminal and said second input/output terminal;
a second field effect transistor inserted in series between said first input/output terminal and said third input/output terminal;
a third field effect transistor connected between said second input/output terminal and said fixed potential terminal;
a fourth field effect transistor connected between said third input/output terminal and said fixed potential terminal;
a first resistor connected between said fixed potential terminal and said first input/output terminal;
a second resistor connected between said fixed potential terminal and said second input/output terminal; and
a third resistor connected between said fixed potential terminal and said third input/output terminal, wherein said first, second and third resistors have resistance values smaller than the resistance values of said third and fourth field effect transistors at OFF state.
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Abstract
Disclosed is a switch circuit comprising one common input/output terminal, two switching input/output terminals, series field effect transistors respectively inserted between the common input/output terminal and the two switching input/output terminals, shunt field effect transistors respectively inserted between the two switching input/output terminals and the ground, and resistors respectively inserted between the ground and the common input/output terminal and between the ground and the two switching input/output terminals, the resistors having the resistance values smaller than that of the shunt field effect transistors at OFF state.
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Citations
10 Claims
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1. A switch circuit comprising:
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a first input/output terminal; a second input/output terminal; a third input/output terminal; a fixed potential terminal; a first field effect transistor inserted in series between said first input/output terminal and said second input/output terminal; a second field effect transistor inserted in series between said first input/output terminal and said third input/output terminal; a third field effect transistor connected between said second input/output terminal and said fixed potential terminal; a fourth field effect transistor connected between said third input/output terminal and said fixed potential terminal; a first resistor connected between said fixed potential terminal and said first input/output terminal; a second resistor connected between said fixed potential terminal and said second input/output terminal; and a third resistor connected between said fixed potential terminal and said third input/output terminal, wherein said first, second and third resistors have resistance values smaller than the resistance values of said third and fourth field effect transistors at OFF state. - View Dependent Claims (2, 3, 4, 5)
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6. A transistor switch comprising:
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a first input/output terminal; a second input/output terminal; a reference terminal held at a fixed potential; a first field effect transistor inserted in series between said first input/output terminal and said second input/output terminal; a second field effect transistor inserted between said second input/output terminal and said reference terminal; and first and second resistors respectively connected between said reference terminal and said first input/output terminal and between said reference terminal and said second input/output terminal and having resistance values smaller than that of said second field effect transistor at OFF state. - View Dependent Claims (7, 8, 9, 10)
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Specification