High performance integrated circuit packaging structure

• US 4,811,082 A
• Filed: 11/12/1986
• Issued: 03/07/1989
• Est. Priority Date: 11/12/1986
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jacobs, Scott L., Ozmat, Burhan, Schnurmann, Henri D., Nihal, Perwaiz
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/929,946
• Time in Patent Office: 846 Days
• Field of Search: 357/80, 357/75, 357/74, 174/68.5
• US Class Current: 257/700
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures. The preferred embodiment comprises an interposer having a base substrate having alternating insulation and conductive layers thereon, wherein a plurality of the conductive layers are wiring means which are adapted for maintaining an extremely low noise level in the package. The low noise level and low resistance and capacitance of the wiring means allows a plurality of discrete semiconductor segments to be mounted on and interconnected by the integrated circuit package with a significantly reduced number of drivers and receivers than required by Rent'"'"'s Rule. Each integrated circuit structure of the present invention emulates a large chip or wafer scale integration structure in performance without having to yield the large chip or wafer, and without redundancy schemes. A plurality of these integrated circuit packaging structures are combined by decals to form a central processing unit of a computer or a portion thereof. In an alternate preferred embodiment, the base substrate of the interposer is made of silicon and any required drivers are formed therein, thus substantially eliminating the need for any drivers on each of the discrete semiconductor segments.

Claims

1. A high performance integrated circuit packaging structure comprising:

a substrate;

alternating insulation and conductive layers on said substrate;

a plurality of internal circuits integrated into discrete semiconductor segments;

said discrete semiconductor segments mounted on an uppermost conductive layer;

said semiconductor segments placed in close enough proximity to each other so that performance is equal to that of a monolithic integrated circuit structure;

an array of feedthroughs in said substrate, a plurality of said feedthroughs located beneath said semiconductor segments;

wiring means incorporated into at least two of said conductive layers for providing connections for said internal circuits;

said wiring means being adapted for maintaining a noise voltage level in said integrated circuit structure which is substantially less than the lowest logic threshold voltage in said integrated circuit structure so that said plurality of internal circuit groups collectively have a number of drivers and receivers which is less than the number provided for by Rent'"'"'s Rule.

2. The packaging structure of claim 1 wherein said wiring means are comprised of at least two layers, each layer having substantially coplanar power and signal lines, wherein substantially all of said substantially coplanar signal lines are separated from each other by at least one substantially coplanar power line, and

said power lines of each layer are electrically interconnected so that the voltage levels of any two interconnected power lines are the same, whereby at least one power plane at a particular voltage level exists in three dimensions.

3. The packaging structure of claim 1 wherein said substrate is made of a semiconductor material.

4. The integrated circuit packaging structure of claim 1 wherein said wiring means comprise a plurality of signal wiring lines and power distribution structures.

5. The integrated circuit packaging structure of claim 1 wherein said plurality of internal circuit groups collectively has a number of drivers and receivers which is less than the number provided for by Rent'"'"'s Rule, and greater than or equal to the following expression:

##EQU4## wherein n is equal to said plurality of internal circuit groups;

S=the number of drivers and receivers required according to Rent'"'"'s Rule;

Cm is equal to the number of logic circuits in each internal circuit group, and

R=Rent'"'"'s exponent.

6. The integrated circuit packaging structure of claim 2 wherein said plurality of internal circuit groups collectively has a number of drivers and receivers which is less than the number provided for by Rent'"'"'s Rule, and greater than or equal to the following expression:

##EQU5## wherein n is equal to said plurality of internal circuit groups;

S=the number of drivers and receivers required according to Rent'"'"'s Rule;

Cm is equal to the number of logic circuits in each internal circuit group, and

R=Rent'"'"'s exponent.

7. The integrated circuit packaging structure of claim 1 wherein said wiring means provide a ratio of lowest signal threshold voltage to coupled noise plus delta-I noise of greater than or equal to approximately 10 to 1.

8. The integrated circuit packaging structure of claim 2 wherein said wiring means provide a ratio of lowest signal threshold voltage to coupled noise plus delta-I noise of greater than or equal to approximately 10 to 1.

9. The packaging structure of claim 3 wherein said substrate is made of silicon.

10. The packaging structure of claim 1 wherein said semiconductor segments are mounted to said uppermost conductive layer by solder balls between approximately 1 and 3 mils in diameter.

11. The packaging structure of claim 9 wherein there are signal feedthroughs through said silicon, said signal feedthroughs comprising;

a central conductor, a low expansion dielectric substantially surrounding said conductor, and an insulator surrounding said low expansion dielectric.

12. The packaging structure of claim 11 wherein said low expansion dielectric is polyimide.

13. The packaging structure of claim 1 wherein said array of feedthroughs is comprised of substantially all power feedthroughs.

14. The packaging structure of claim 1 wherein said array of feedthroughs is comprised of both signal and power feedthroughs.

15. The packaging structure of claim 2 wherein said signal wiring lines are between approximately 3 and 10 microns wide, and between approximately 3 and 10 microns tall.

16. The packaging structure of claim 15 wherein said signal and power lines are spaced between approximately 5 and 10 microns apart.

17. The integrated circuit packaging structure of claim 1 further comprising at least one other of said integrating circuit packaging structures, said structures being connected to each other and to a mother substrate.

18. The packaging structure of claim 17 wherein said mother substrate is a multi-layered ceramic substrate.

19. The packaging structure of claim 17 wherein said connections between said integrated circuit packaging structures are made by decals.

20. The packaging structure of claim 19 wherein said decals comprise a flexible carrier layer having at least one signal wiring layer and one ground layer therein.

21. The packaging structure of claim 3 wherein at least one of said drivers is present in said semiconductor substrate.

22. The packaging structure of claim 17 wherein said substrate is made of a semiconductor material.

23. The packaging structure of claim 22 wherein at least one of said drivers is present in said semiconductor substrate.

24. The packaging structure of claim 3 wherein there are substantially no drivers in said discrete semiconductor segments, and a plurality of drivers in said semiconductor substrate.

25. The packaging structure of claim 22 wherein there are substantially no drivers in said discrete semiconductor segments, and a plurality of drivers in said semiconductor substrate.