Multiple microprocessor watchdog system

• US 4,811,200 A
• Filed: 05/12/1987
• Issued: 03/07/1989
• Est. Priority Date: 05/12/1987
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Wagner, David J., Picha, Dean M., Laping, Robert J., Oller, Stephen G.
• Primary Examiner(s): Williams, Jr., Archie E.
• Assistant Examiner(s): MOHAMED, AYNI Y
• Application Number:
  US07/049,769
• Time in Patent Office: 665 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 371/62
• US Class Current: 714/23
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/1415 at system level
• CPC Class Codes: G06F 11/32 with visual or acoustical indication of the functioning of the machine

Abstract

A main microprocessor A (11) provides data to a display formatter microprocessor B (12) via a data bus (13). Microprocessor B provides data and latch (activity) pulses (34A) to a visual display (27) comprising a number of individual display devices (28-30) which are sequentially excited by data obtained from microprocessor B. An external activity detector (38), in response to an absence of the latch pulses of microprocessor B for a predetermined time, generates a reset signal (40) for resetting the microprocessor A. In response to being reset, microprocessor A provides an output control signal (at 20) which results in the resetting of the microprocessor B. If microprocessor B determines that microprocessor A is not properly providing data to it, microprocessor B will terminate generating the latch pulses (34A). The preceding configuration results in each of the microprocessors effectively monitoring the operation of the other microprocessor so as to insure proper system operation. Therefore, this system properly resets itself in response to any of a large number of different failures which may occur in either of the microprocessors, and this is accomplished with a minimum of additional hardware circuitry and software programming.

Claims

1. A multiple microprocessor watchdog system comprising:

first microprocessor means A for generating output data on a first data bus and having an input reset terminal and an output control terminal, a control signal being provided at said output control terminal by said microprocessor means A in response to said microprocessor means A being reset;

second microprocessor means B coupled to said microprocessor means for receiving said data on said first data bus, processing said output data and providing said processed output data on a second data bus, said microprocessor means B having a reset input terminal, said microprocessor means B also having an activity output terminal at which activity pulses are periodically provided by said microprocessor means B, the existence of said periodic activity pulses being indicative of proper operation of said microprocessor means B;

utilization means coupled to said microprocessor means B for receiving and utilizing said processed output data on said second data bus; and

activity detector means coupled to said activity output terminal of said microprocessor means B for receiving said periodic activity pulses and providing a reset signal at an output terminal of said activity detector means in response to an absence of said periodic activity pulses;

the improvement comprising,

said reset output terminal of said activity detector means being coupled to the reset input terminal of said microprocessor means A, and the control output terminal of microprocessor means A being connected to the reset input terminal of microprocessor means B, wherein detected activity failures of microprocessor means B result in said reset signal provided by said activity detector means resetting microprocessor means A and said microprocessor means A then resetting microprocessor means B.

2. A multiple microprocessor watchdog system according to claim 1 wherein said microprocessor means B includes means for detecting when microprocessor means A is not properly sending data via said first data bus to microprocessor means B and, in response thereto, terminating generating said periodic activity pulses, whereby microprocessor means A and microprocessor means B are then reset.

3. A multiple microprocessor watchdog system according to claim 2 wherein said utilization means comprises a visual display means for providing visual displays indicative of said received processed output data on said second data bus.

4. A multiple microprocessor watchdog system according to claim 3 wherein said display means includes display driver means for periodically distributing said received processed output data to various separate visual display devices in said display means in accordance with multiplex signals received by said display driver means.

5. A multiple microprocessor watchdog system according to claim 4 wherein said output terminal of said microprocessor means B is effectively connected to said display means, and wherein strobe excitation of said display devices is derived from said periodic activity pulses provided at said output terminal of said microprocessor means B.

6. A multiple microprocessor watchdog system according to claim 5 wherein a blanker circuit means is provided in said display means, said blanker circuit means, in response to an absence of activity pulses at said output terminal of said microprocessor means B for a predetermined time, causes said display driver means to provide a blank visual display on said visual display devices.

7. A multiple microprocessor watchdog system according to claim 6 wherein said display devices comprise vacuum fluorescent display devices.

8. A multiple microprocessor watchdog system according to claim 2 wherein said microprocessor means A provides a data available signal, separate from said data on said data first bus, to said microprocessor means B, and wherein said microprocessor means B includes means for terminating the generation of said activity pulses in response to the absence of said data available signal for a predetermined time.

9. A multiple microprocessor watchdog system according to claim 2 wherein said microprocessor means A includes means therein for internally resetting itself in response to said microprocessor means A failing to perform expected functions within a predetermined time period.

10. A multiple microprocessor watchdog system according to claim 2 wherein said activity detector means comprises a circuit separate from said microprocessor means A and B, whereby program faults in either microprocessor means are less likely to prevent proper operation of the activity detector means.

11. A multiple microprocessor watchdog system according to claim 3 wherein said microprocessor means A is reset in response to each application of power thereto, and wherein immediately after reset said microprocessor sends predetermined initial blank visual data to said microprocessor means B to insure an initial blank visual display after power applied to microprocessor means A, whereby undesired visual display flickering can be minimized for applied power transients.

12. A multiple microprocessor watchdog system according to claim 1 wherein said microprocessor means B is effectively disabled by said control signal during the resetting of microprocessor means A to prevent microprocessor means B from responding to transient outputs of microprocessor means A during the resetting of microprocessor means A.

13. A multiple microprocessor watchdog system comprising:

first microprocessor means A for generating output data on a first data bus and having an input reset terminal and an output control terminal, a control signal being provided at said output control terminal by said microprocessor means A in response to said microprocessor means A being reset;

second microprocessor means B coupled to said microprocessor means A for receiving said data on said first data bus, processing said output data and providing said processed output data on a second data bus, said microprocessor means B having a reset input terminal, said microprocessor means B also having an activity output terminal at which activity pulses are periodically produced by said microprocessor means B as long as said microprocessor means B is operating properly, the existence of said periodic activity pulses being indicative of proper operation of said microprocessor means B;

utilization means coupled to said microprocessor means B for receiving and utilizing said processed output data on said second data bus; and

activity detector means coupled to said activity output terminal of said microprocessor means B for receiving said periodic activity pulses and providing a reset signal at an output terminal of said activity detector means in response to an absence of said periodic activity pulses;

the improvement comprising,

said reset output terminal of said activity detector means being coupled to the reset input terminal of said microprocessor means A, and the control output terminal of microprocessor means A being connected to the reset input terminal of microprocessor means B, wherein detected activity failures of microprocessor means B result in said reset signal provided by said activity detector means resetting microprocessor means A and said microprocessor means A then resetting microprocessor means B.