Quadruply extended time multiplexed information bus for reducing the `pin out` configuration of a semiconductor chip package

• US 4,811,202 A
• Filed: 10/01/1981
• Issued: 03/07/1989
• Est. Priority Date: 10/01/1981
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Schabowski, John
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/307,415
• Time in Patent Office: 2,714 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/307
• CPC Class Codes: G06F 1/22 Means for limiting or controlling the pin/gate ratio
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A digital processor system includes a processor, a memory and a memory interface between the processor and the memory. The memory stores data in one bit format but addresses the data in a second bit format. The interface to the memory includes a controller that is responsive to the processor, an information bus for the transfer of addresses and data and two registers to store addresses for the memory. These registers in the interface are responsive to the processor through the interface controls in order to allow the processor to increment or decrement the memory addresses or load new memory addresses from the information bus. These registers are then connected to a switch which is in turn responsive to the processor through the interface control in order that the processor can determine which register is to provide the address to the memory.

Claims

1. A digital processor system comprising:

processor means for processing of data according to program instructions;

memory means including a memory array means for storing according to memory addresses, the data and program instructions;

Interface means coupled between said processor means and said memory means for transferring the data and programmed instructions, said interface means comprising;

control means responsive to said processor means and said memory means for providing control signals in response to the processor means and said memory means;

a quadruply extended time multiplex information bus means having a first preselected number of bits in width for transferring data and program instructions having a second preselected number of bits in width greater that the first preselected number of bits between said processor means and said memory means;

memory addressing means coupled to said quadruply extended time multiplex information bus for receiving memory address and the data and programs instructions and includes;

a first register means for providing memory address of the data to the memory array means, a second register means for providing memory addresses of the program instructions to the memory array means, boththe first and second register means being coupled to said control means and in response to the control signals alter the contents of said first and second register means by incrementing or decrementing the register contents of the first register means, switch means for connecting either the first or second register means to the memory array means in response to a preselected member of the control signals to store the data and program instructions in the memory array means thereby.

2. A digital processor system according to claim 1, wherein said control signals include an address strobe signal, data strobe signal and a program counter signal coupled to said switch means to allow either the memory address stored in said first register means or in said second register means to be coupled to said memory means.

3. A digital processor system according to claim 2, wherein said first register of said memory addressing means may be incremented upon occurrence of the data strobe signal.

4. A digital processor system according to claim 2, wherein said control signals further include a read/write signal and a memory enable signal from said processor means and a ready signal from said memory means.

5. A digital processor system according to claim 1, wherein said control signals include a load address signal coupled to said first register to provide decrementing capability.