Multinode reconfigurable pipeline computer

• US 4,811,214 A
• Filed: 11/14/1986
• Issued: 03/07/1989
• Est. Priority Date: 11/14/1986
• Status: Expired due to Fees

• Current Assignee: Princeton University
• Original Assignee: Princeton University
• Inventors: Littman, Michael G., Nosenchuck, Daniel M.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Fairbanks, Jonathan C.
• Application Number:
  US06/931,549
• Time in Patent Office: 844 Days
• Field of Search: 364/736, 364/748, 364/749, 364/200 MS File, 364/900 MS File
• US Class Current: 712/11
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead

Abstract

A multinode parallel-processing computer is made up of a plurality of innerconnected, large capacity nodes each including a reconfigurable pipeline of functional units such as Integer Arithmetic Logic Processors, Floating Point Arithmetic Processors, Special Purpose Processors, etc. The reconfigurable pipeline of each node is connected to a multiplane memory by a Memory-ALU switch NETwork (MASNET). The reconfigurable pipeline includes three (3) basic substructures formed from functional units which have been found to be sufficient to perform the bulk of all calculations. The MASNET controls the flow of signals from the memory planes to the reconfigurable pipeline and vice versa. the nodes are connectable together by an internode data router (hyperspace router) so as to form a hypercube configuration. The capability of the nodes to conditionally configure the pipeline at each tick of the clock, without requiring a pipeline flush, permits many powerful algorithms to be implemented directly.

Claims

1. A multi-node, parallel processing computer apparatus comprising:

a plurality of nodes each including an internal memory and a reconfigurable arithmetic logic (ALU) pipeline unit and a memory/ALU/switch network (MASNET) for transferring data from said internal memory through said MASNET to said reconfigurable ALU pipeline unit and from said reconfigurable ALU pipeline unit through said MASNET to said internal memory, said reconfigurable ALU pipeline unit further including a first group of programmable processors permenantly connected together in a first configuration having four (4) inputs and one (1) output and a second group of programmable processors permanently connected together in a second configuration different from said first configuration, said second group having three (3) inputs and one (1) output, and an ALU pipeline configuration switching network means (FLONET) for selectively connecting said first and second groups to each other, and sequencer means for providing instructions to said FLONET once a clock cycle; and

,

router means for routing data between said nodes,

wherein said reconfigurable ALU pipeline unit selectively performs different computations according to instructions from said sequencer means once a clock cycle.

2. A reconfigurable computer apparatus comprising:

a first group of programmable processors permanently connected together in a first configuration having four (4) inputs and one (1) output, said first group including a first programmable processor having at least two (2) inputs and at least one (1) output;

a second programmable processor having at least two (2) inputs and at least one (1) output; and

, a third programmable processor having two (2) inputs permanently connected to the outputs of said first and second programmable processors, said third programmable processor also having an output, such that the four inputs of said first group comprise the inputs of said first and second programmable processors and the output of said first group comprises the output of said third programmable processor;

a second group of programmable processors permanently connected together in a second configuration different from said first configuration, said second group having three (3) inputs and one

     91) output and including a fourth programmable processor having two (2) inputs and one (1) output; and

, a fifth programmable processor having two (2) input and one (1) output, one of said inputs of said fifth programmable processor being permanently connected to the output of said fourth programmable processor, such that the three (3) inputs of said second group comprise the two (2) inputs to said fourth programmable processor and the input to said fifth programmable processor not connected to the output of said fourth programmable processor, and the output of said second group comprising the output of said fifth programmable processor;

a third group or programmable processors comprising individual processors having two (2) inputs and one (1) output;

switching means (FLONET) for selectively connecting said first, second and third groups together; and

,

sequencer means for providing instructions to said FLONET once a clock cycle,

wherein said apparatus selectively performs different computations according to instructions from said sequencer means once a clock cycle.

18. The apparatus of claim 2 further comprising:

an internal memory; and

,

a memory-ALU switch network means (MASNET) for transferring data from said internal memory through said MASNET to said switching means and for transferring data from said switching means through said MASNET to said internal memory.

19. The apparatus of claim 18 wherein said sequences means further comprises:

microsequencer means connected to said internal memory, MASNET and switching means for governing the clocking of data between said internal memory, MASNET and switching means.

20. The apparatus of claim 19 further comprising:

microcontroller means connected to said internal memory, MASNET and switching means for initializing and verifying the status of said internal memory, MASNET and switching means.

21. The apparatus of claim 2 wherein at least some of said processors comprise floating point arithmetic processors.

22. The apparatus of claim 2 wherein at least some of said processors comprise integer arithmetic logic processors.

23. The apparatus of claim 2 wherein the ratio of said first group of programmable processors with respect to said second group of programmable processors is approximately in the range of 1.5-2.0 to 1.0.

24. The apparatus of claim 2 wherein the ratio of said second group of programmable processors to said third group of programmable processors is approximately 2.0 to 1.0.

3. A reconfigurable computer apparatus including arithmetic/logic units (ALU), said apparatus comprising:

at least a first substructure including three (3) ALU units permanently connected together in a first configuration having four (4) inputs and one (1) output;

at least a second substructure including two (2) ALU units permanently connected together in a second configuration having three (3) inputs and one (1) output;

at least a third substructure including at least one individual ALU unit having two (2) outputs and one (1) output;

switching means for selectively connecting said first, second and third substructure together; and

,

sequencer means for providing instructions to said switching means,

wherein said apparatus selectively performs computations according to instructions from said sequencer means.

4. A node apparatus for use in a multi-node, parallel processing system, said node apparatus comprising:

an internal memory including a plurality of memory planes;

a dynamically reconfigurable arithmetic logic (ALU) pipeline means for performing computations, including a plurality of ALUs at least three of which are permanently connected to each other;

an ALU pipeline configuration switching network means (FLONET) for selectively connecting groups of said ALUs in said dynamically reconfigurable arithmetic logic pipeline means together;

a memory/ALU/switch network (dASNET) for transferring data from the memory planes of said internal memory through said MASNET to said dynamically reconfigurable ALU pipeline means and from said dynamically reconfigurable ALU pipeline means through said MASNET to said internal memory; and

,

sequencer means for providing instructions to said FLONET,

wherein said dynamically reconfigurable ALU pipeline means selectively performs different computations according to instructions from said sequencer means.

5. The apparatus of claim 29 wherein said first group of programmable processors comprises:

a first programmable processor having at least two (2) inputs and at least one (1) output;

a second programmable processor having at least two (2) inputs and at least one (1) output; and

,

a third programmable processor having two (2) inputs permanently connected to the outputs of said first and said second programmable processors, said third programmable processor also having an output,

wherein the inputs to said first group comprise the inputs of said first and second programmable processors and the output of said first group comprises the output of said third programmable processor.

6. The apparatus of claim 5 wherein said second group of programmable processors comprise:

a fourth programmable processor having at least two (2) inputs and at least one (1) output; and

,

a fifth programmable processor having two (2) inputs and one (1) output, one of said inputs of said fifth programmable processor being permanently connected to the output of said fourth programmable processor,

wherein the inputs of said second group comprise the two inputs to said fourth programmable processor and the one input to said fifth programmable processor not connected to the output of said fourth programmable processor, and the output of said second group comprises the output of said fifth programmable processor.

7. The apparatus of claim 6 wherein said reconfigurable ALU pipeline unit further comprises:

a third group of programmable processors comprising individual programmable processors connected to said FLONET for selective connection with said first and second groups of programmable processors.

8. The apparatus of claim 7 wherein the ratio of said first group of programmable processors with respect to said second group of programmable processors in a given reconfigurable ALU pipeline unit is approximately in the range of 1.5-2.0 to 1.0.

9. The apparatus of claim 8 wherein the ratio of said second group of programmable processors to said third group of programmable processors is approximately 2.0 to 1.0.

10. The apparatus of claim 9 wherein said internal memory comprises a plurality of memory planes.

11. The apparatus of claim 10 wherein each memory plane comprises:

a main memory bank;

an address multiplexer for transmitting data to and from said main memory bank;

a prefetch address register connected between said main memory bank and said address multiplexer; and

,

a translate table means connected to said address multiplexer for scanning said assembly bank in a random access manner.

12. The apparatus of claim 11 wherein said sequencer means further comprises:

microsequencer means connected to said internal memory, MASNET and reconfigurable ALU pipeline unit for governing the clocking of data between said internal memory, MASNET and said reconfigurable ALU pipeline unit.

13. The apparatus of claim 12 wherein each node further comprises:

a microcontroller connected to said internal memory, MASNET and said reconfigurable ALU pipeline unit for initializing and verifying the status of said internal memory, MASNET and reconfigurable ALU pipeline.

14. The apparatus of claim 13 wherein said MASNET comprises:

a plurality of register files cross connected in a Benes switching network arrangement and pipelined so as to make the connection of any input to any output non-blocking.

15. The apparatus of claim 14 further comprising:

boundary-point definition (BPD) cache means connected between said router means and said MASNET for routing BPD data to specific destination nodes,

wherein said apparatus supports both global addressing and explicit BPD addressing modes.

16. The apparatus of claim 15 further comprising:

a front end computer for feeding data and instructions to said nodes; and

,

off-line mass storage means connectable to said front end computer.

17. The apparatus of claim 16 wherein said nodes are connected together in the topology of a boolean hypercube and vary in number in the range of from 1 to 128.