Structured design method for generating a mesh power bus structure in high density layout of VLSI chips

• US 4,811,237 A
• Filed: 06/24/1987
• Issued: 03/07/1989
• Est. Priority Date: 06/19/1987
• Status: Expired due to Fees

• Current Assignee: Martin Marietta Corporation
• Original Assignee: General Electric Company
• Inventors: Smith, David C., McNeary, Stephen A., Putatunda, Rathindra N.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Trans, V. N.
• Application Number:
  US07/065,998
• Time in Patent Office: 622 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/127
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

An automated LSI chip layout arrangement includes automated layout of the power bus distribution network. A complete interlocking mesh of buses is run in routing channels lying between groups of circuits to be powered. Each segment of the mesh powering net which affects the chip size is tested to see if it can be removed without adversely affecting the power distribution. If it can be removed, the segment is deleted. The next segment which is critical to the size of the chip is then tested, and the process is continued. Those segments of the power bus distribution network which do not affect the size of the chip are not eliminated. Thus, a low-resistance power distribution bus network is guaranteed, and chip size is minimized.

Claims

1. A method for layout of a power bus distribution structure for the target surface of a large scale integrated circuit which includes macrocells and domains of standard logic cells arranged in rows, comprising the steps of:

predetermining minimum values of source factor for all standard cell domains and macrocells to produce predetermined minimum values;

generating a complete power bus distribution structure including routing channels associated with elements of said complete power bus distribution structure, said routing channels being adjacent the sides of macrocells and standard cell domains, said routing channels being adapted for carrying signal wires and wires of said power bus distribution structure;

determining those routing channels which are critical to the size of said target area to identify critical routing channels;

selecting one of said critical routing channels to identify a selected critical routing channel;

creating, if not already created, a profile of signal wire routing density for at least said selected critical routing channel;

subdividing into segments at least that portion of said power bus distribution structure routed through said selected critical routing channel, said segments having ends intersecting orthogonal portions of said power bus distribution structure;

identifying as a highest density segment, from among said segments of said power bus distribution system routed through said selected critical routing channel, that one segment not yet processed which is associated with the largest of said signal wire routing densities;

temporarily deleting said highest density segment of said power bus distribution structure from said power bus distribution structure to form a temporarily segment pruned power bus distribution structure;

calculating the present source factors for the macrocells and standard cell domains of said temporarily segment pruned power bus distribution structure;

comparing said present source factors of said macrocells and standard cell domains of said temporarily segment pruned power bus distribution structure with said predetermined minimum values, and if any one of the present source factors is less than the corresponding predetermined minimum value, restoring said temporarily deleted highest density segment, and if said present source factors of said macrocells and standard cell domains are all greater than their corresponding predetermined minimum values, permanently deleting said highest density segment to produce a segment pruned power bus distribution structure;

repeating said step of (a) identifying as a highest density segment, (b) temporarily deleting, (c) calculating and (d) comparing, until all power bus segments within said selected critical routing channel have been processed to form a routing channel pruned bus distribution structure; and

repeating said steps of (a) determining those routing channels which are critical, (b) selecting one of said critical routing channels, (c) creating a profile, (d) subdividing into segments, (e) identifying as a highest density segment, (f) temporarily deleting, (g) calculating, (h) comparing, and (i) repeating, until no further pruning is possible.

2. A method according to claim 1 wherein said large scale integrated circuit is provided with at least first and second different metallization levels, and wherein said step of generating a complete power bus distribution structure comprises the steps of:

grouping together standard logic cells to produce standard cell domains;

identifying macrocells as domains;

generating lower level superdomains by grouping together standard cell domains with other standard cell domains, standard cell domains with macrocells, and macrocells with macrocells;

generating higher level superdomains by grouping lower level superdomains with standard cell domains, macrocells or other lower level superdomains;

placing macrocells and standard cell domains on said target surface in a right-left, top-bottom topological configuration, with vertical and horizontal interdomain channels between adjacent domains, between adjacent superdomains, between superdomains and domains, between superdomains and macrocells, and between macrocells and domains, whereby said interdomain channels may be vertical or horizontal;

inscribing within the outermost boundary of said target area with a pair of parallel first metallization level positive and negative primary power buses to form a primary portion of said power bus distribution structure;

placing input-output signal buffer circuits adjacent said outermost boundary of said target area, and connecting said signal buffer circuits to said pair of first metallization level positive and negative primary power buses;

providing at least one pair of power bonding pads, at each of first and second locations about said outermost boundary of said target area, each of said pairs of power bonding pads including a positive power bonding pad connected at a positive power supply node to said positive primary power bus, and also including a negative power bonding pad connected at a negative power supply node to said negative primary power bus;

identifying a secondary region of said target area surrounded by said primary buses;

inscribing within the outermost boundary of said secondary region a pair of parallel positive and negative secondary power buses, those portions of said secondary power buses directed vertically being at one of said first and second metallization levels, and those portions of said secondary power buses directed horizontally being at the other one of said first and second metallization levels;

connecting said positive and negative primary power buses to those of said positive and negative secondary power buses, respectively, which are at the same one of said first and second metallization levels;

connecting said positive and negative secondary power buses at the other one of said first and second metallization levels, by way of through vias, to said positive and negative secondary power buses, respectively, which are at said one of said first and second metallization levels;

defining a complete tertiary power bus distribution structure within the region bounded by said secondary power buses, said tertiary power bus distribution structure including a pair of tertiary positive and negative buses routed at said one of said first and second metallization levels through each of said vertical interdomain channels, and a pair of tertiary positive and negative power buses routed at said other one of said first and second levels through each of said horizontal interdomain channels;

interconnecting said tertiary power buses at said other level by way of through vias with said secondary and tertiary power buses at said one level only at locations which are at the extreme end of at least one of said secondary and tertiary power buses, said tertiary positive power buses being interconnected with secondary positive buses and also being interconnected with other tertiary positive power buses, and tertiary negative power buses being interconnected with secondary negative power buses, and also being interconnected with other tertiary negative power buses;

routing quarternary conductors from said secondary and tertiary buses to said macrocells and to the rows of said standard logic cells in said standard logic cell domains.

3. A method according to claim 2 wherein said quartenary conductors running vertically are formed at said one of said first and second metallization levels, and said quartenary conductors running horizontally are formed at the other one of said first and second metallization levels.

4. A method according to claim 3 wherein said rows of standard logic cells in said standard cell domains are all oriented horizontally, and said quartenary conductors coupled to said standard cell domains are horizontal runs to at least one end of each of said rows of standard logic cells.

5. A method according to claim 2, wherein said step of calculating the present source factors for the macrocells and standard cell domains comprises the further step of:

counting the number of said positive and negative power bonding pad pairs which can supply power to the one of said macrocells and standard cell domains under consideration directly and not by way of one of a further power bonding pad pair and equivalents of a further power bonding pad pair.

6. A method according to claim 1, wherein said step of predetermining minimum values of source factor comprises the steps of:

determining the maximum current drain of each macrocell and standard cell domain;

for each macrocell and standard cell domain, establishing the number N of whole or partial increments of A amperes of current which are included in said maximum current drain; and

assigning N as the source factor of the circuit under consideration.

7. A method according to claim 6 wherein said increment of A amperes is 1/4 ampere.

8. A method according to claim 1, wherein said step of creating a profile of signal routing density is performed for all routing channels preceding said step of determining those routing channels which are critical to the size of said target area.

9. A method according to claim 8, wherein said target area is subdivided by a coordinate system of orthogonal grid lines, and wherein said step of creating a profile of said routing density comprises the step of counting the number of wires within each routing channel intersecting each grid line orthogonal to the length of each segment of said routing channel.

10. A method according to claim 1 wherein said step of subdividing into segments is performed preceding said step of determining those routing channels which are critical to the size of said target area, and said step of subdividing into segments is performed for all critical routing channels.

11. A method according to claim 10 wherein said step of subdividing into segments includes the further steps of:

for each critical routing channel, determining the locations of the intersections with orthogonal routing channels; and

identifying as a segment (a) that portion of each wiring channel lying between two adjacent intersections and (b) tat portion of each routing channel lying between an end of each routing channel and an adjacent intersection.

12. A method according to claim 1, wherein said large scale integrated circuit is laid out as an assemblage of left-right, top-bottom combinations of nodes of progressive order defining a binary tree, each parent node of which is formed from only two daughter elements, and wherein said step of determining those routing channels which are critical to the size of said target area comprises the further steps of:

determining the height and width of said target area;

determining the height and width of each of said routing channels;

identifying as the root critical routing channel that routing channel lying between the daughter nodes of the root node of said binary tree;

determining which daughter node includes the next lower order critical routing channel by selecting that daughter node which is widest for top-bottom placed daughter nodes, and by selecting that daughter node which is tallest for right-left placed daughter nodes, to produce a selected daughter node;

identifying as another critical routing channel that channel associated with said selected daughter node; and

repeating said steps of (a) determining which daughter node and (b) said identifying as another critical routing channel, steps until said selected daughter node is a leaf node of said binary tree.

13. A method according to claim 1 wherein said step of selecting one of said routing channels which is critical to the size of said target area comprises the further step of:

ordering said routing channels according to length; and

identifying as said selected critical routing channel that one routing channel having the greatest length, and if a plurality have said greatest length, identifying as said selected critical routing channel that one having the greatest number of segments.

14. A method according to claim 1, wherein said target area is subdivided by a coordinate system of orthogonal grid lines, and wherein said step of creating a profile of said routing density comprises the step of counting the number of wires within each routing channel intersecting each grid line orthogonal to the length of each segment of said routing channel.

15. A method according to claim 1 wherein said step of subdividing into segments includes the further steps of:

for each critical routing channel, determining the locations of the intersections thereof with orthogonal routing channels; and

identifying as a segment (a) that portion of each wiring channel lying between two adjacent intersections and (b) that portion of each routing channel lying between an end of each routing channel and an adjacent intersection.

16. A method according to claim 1, wherein said target area is subdivided by a coordinate system of orthogonal grid lines, and wherein said step of identifying as a highest density segment comprises the further steps of:

counting the number of wires within each segment intersecting each of said grid lines which is orthogonal to the length of said segment of said routing channel;

for each segment of said routing channel, identify that one segment containing the maximum number of wires intersecting a grid line as said highest density segment; and

selecting that one power bus segment associated with said highest density routing channel segment as a highest density segment.