Analog storage integrated circuit
First Claim
1. A high speed data acquisition system for storing a succession of analog signal sample values comprising analog signal input means and analog signal output means, a first analog input bus connected to said analog signal input means and a second analog output bus connected to said analog signal output means, a storage array comprising a plurality of cells arranged in rows and columns, row clock means coupled to said storage array for selectively activating each row of said storage array, column clock means coupled to said storage array for selectively activating each column of said storage array, said analog signal input means being directly connected to said storage array for supplying an analog signal to the cells of the array, and means responsive to the row and column clock means for successively activating each of said cells for storing a succession of analog signal sample values comprising samples of said analog signal, each of said cells comprising a pair of gates connected between said analog signal input means and a first capacitor in said cell for causing said first capacitor to store each said analog signal sample value, said gates being responsive to said row and column clock activating means, each of said cells comprising a voltage follower coupled to said first capacitor, and a multiplex output device connected between said voltage follower and said second analog output bus for transferring a proportional represntation of each said stored analog signal sample value to said output bus.
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Abstract
A high speed data storage array is defined utilizing a unique cell design for high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates between the signal input and a storage capacitor. The gates are controlled by a high speed row clock and low speed column clock so that the instantaneous analog value of the signal is only sampled and stored by each cell on coincidence of the two clocks.
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Citations
19 Claims
- 1. A high speed data acquisition system for storing a succession of analog signal sample values comprising analog signal input means and analog signal output means, a first analog input bus connected to said analog signal input means and a second analog output bus connected to said analog signal output means, a storage array comprising a plurality of cells arranged in rows and columns, row clock means coupled to said storage array for selectively activating each row of said storage array, column clock means coupled to said storage array for selectively activating each column of said storage array, said analog signal input means being directly connected to said storage array for supplying an analog signal to the cells of the array, and means responsive to the row and column clock means for successively activating each of said cells for storing a succession of analog signal sample values comprising samples of said analog signal, each of said cells comprising a pair of gates connected between said analog signal input means and a first capacitor in said cell for causing said first capacitor to store each said analog signal sample value, said gates being responsive to said row and column clock activating means, each of said cells comprising a voltage follower coupled to said first capacitor, and a multiplex output device connected between said voltage follower and said second analog output bus for transferring a proportional represntation of each said stored analog signal sample value to said output bus.
- 15. A method of very high frequency analog pulse sampling of an analog signal supplied to an array of cells arranged in n rows and m columns, comprising selectively activating each said row of said array while each of said columns is activated selectively, to cause each said cell to store a sample of said analog signal, supplying an analog input signal to the cells of the array, said rows being activated for a time interval defining a minimum pulse sampling interval of said analog input signal, said row activating step comprising activating alternate ones of n rows in a pulse sampling cycle wherein all of said rows are activated, n being the number of rows in the array, the rows 1 through n/2 being interleaved with the rows (n/2)+1 to n during said cycle and being activated in numerical order to reduce the sampling spacing time limit caused by propagation delay in column clock signals activating said cells in said columns.
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18. A method as claimed in cliam 17 further comprising the step of providing a reference cell identical in construction to the cells in said array but not receiving said supplied analog signal, the method including the step of reading the output of each cell as a differential output compared to an output of the refernce cell whereby leakage and offset are taken into account.
Specification