Via connection with thin resistivity layer

• US 4,812,419 A
• Filed: 04/30/1987
• Issued: 03/14/1989
• Est. Priority Date: 04/30/1987
• Status: Expired due to Fees

• Current Assignee: HP Inc.
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Nishi, Yoshio, Lee, Keunmyung
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Pawlikowski, Beverly A.
• Application Number:
  US07/045,002
• Time in Patent Office: 684 Days
• Field of Search: 437/192, 437/200, 437/194, 437/203, 338/195, 307/306, 357/67, 427/102
• US Class Current: 438/625
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A via connection and method for making the same for integrated circuits having multiple layers of electrically conductive interconnect lines separated by an insulative layer. The via connection is characterized by a very thin layer of high resistivity material lining the via hole in conductive contact with interconnect lines in two layers. The resistivity of the thin layer material is in a range from about 10 to about 50 times the interconnect line resistivities and generally has a thickness of less than 100 nanometers. The thin layer assures more uniform current flow in the via connection thereby preventing electromigration, with reduced peak local current density by causing current to swing more widely around the corner at the interface between the interconnect lines at the via.

Claims

1. A method of forming via connections in an integrated circuit comprising,

forming a first level of first electrically conductive lines connected to individual circuit elements on a semiconductor chip,

applying a layer of insulative material on said first level,

creating a plurality of holes in said layer of insulative material, said holes being formed over and exposing portions of said first electrically conductive lines,

depositing a thin layer of electrically conductive material in said holes, said thin layer contacting said first conductive lines, said thin layer characterized by a resistivity in a range from about 10 to about 50 times a resistivity of said first conductive lines and a thinness in a range of between 50 nanometers and 100 nanometers, and

forming a second level of second electrically conductive lines, said second lines extending into said holes into contact with said thin layer, said second lines having a resistivity which is approximately equal to said resistivity of said first lines,

whereby said thin layer of electrically conductive material in said holes determines local current density of a current conducted through said holes between said first lines to said second lines.

2. The method of claim 1 wherein said resistivities of said first and second lines are less than 8 μ

Ω

-cm.

3. The method of claim 2 wherein said first and second lines are composed of metallic material selected from the group consisting of aluminum and gold.

4. The method of claim 1 wherein said first and second lines are formed to both a width and thickness of at most 1.0 μ

m.

5. The method of claim 1 wherein said thin layer is deposited over said layer of insulative material.

6. The method of claim 1 wherein said thin layer is composed of electrically resistive metallic material selected from the group consisting of lead, and alloys containing at least two of nickel, chromium, iron, copper, manganese, tungsten and silicides of these.

7. The method of claim 1 wherein said holes are formed in said layer of insulative material by applying a resist layer to said layer of insulative material, patterning hole areas in said resist with a mask, removing said hole areas, and etching said layer of insulative material where said hole areas of said resist have been removed.

8. The method of claim 1 wherein holes formed in said layer of insulative material have a diameter of at most 1.0 μ

m.

9. A method of forming via connections in integrated circuit wafers comprising,

forming a first metal layer of first electrically conductive lines connected to individual circuit elements on a patterned semiconductor wafer having a first insulative layer thereover, said first lines characterized by a line resistivity,

applying a second layer of insulative material over said first metal layer,

patterning a plurality of via holes in said second insulative layer, said via holes being located above and exposing selected portions of said first lines,

applying a thin layer of electrically resistive material over said layer of insulative material, said thin layer extending into and lining the bottom of said via holes and contacting said exposed selected portions of said first lines, the thin layer characterized by a resistivity in a range from about 10 to about 50 times said line resistivity and a thinness in a range of between 50 nanometers and 100 nanometers, and

forming a second metal layer of second electrically conductive lines, said second lines extending into said holes into contact with said thin layer, said second lines characterized by a resistivity approximately equal to said line resistivity of said first lines,

whereby said thin layer acts to control peak current density about said via holes when current is conducted within an integrated circuit wafer.

10. The method of claim 9 wherein said resistivities of said first and second lines are less than 8 μ

Ω

-cm.

11. The method of claim 10 wherein said first and second lines are composed of metal selected from the group consisting of aluminum and gold.

12. The method of claim 9 wherein said thin layer is composed of material selected from the group consisting of lead, and alloys containing a total of at least 75% of at least two of the metals nickel, chromium, iron, copper, and manganese, tungsten and silicides of these.