Gyrator circuit simulating an inductance and use thereof as a filter or oscillator

• US 4,812,785 A
• Filed: 07/24/1987
• Issued: 03/14/1989
• Est. Priority Date: 07/30/1986
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Pauker, Vlad
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US07/077,572
• Time in Patent Office: 599 Days
• Field of Search: 333/214, 333/215, 331/117 R, 331/117 FE, 331/167
• US Class Current: 331/117.0FE
• CPC Class Codes: H03H 11/08 using gyrators
• CPC Class Codes: H03H 11/42 Gyrators used in frequency selective networks H03H11/08
• CPC Class Codes: H03H 11/50 using gyrators

Abstract

A gyrator circuit usable in a resonant filter circuit comprises a first and a second transconductance amplifier circuit, A and B, respectively, having opposite conductances, which amplifiers are arranged in parallel between a first terminal a and a second terminal b and comprise a first capacitance C₁ arranged between said first terminal a and an earth terminal m, which gyrator circuit simulates an inductance L_g arranged between said second terminal b and said earth terminal m and comprises means for controlling the quality factor Q of said inductance, characterized in that the first transconductance amplifier circuit A comprises two series-connected inverting amplifier stages P₁ and P₂, in that the second transconductance amplifier circuit B comprises an inverting amplifier stage P₃, and in that the means for controlling the quality factor Q comprise a first means P₅ for influencing the output conductance q₂ of the gyrator and a second means P₆ for influencing the phase shift between the output current and the control voltage of the gyrator.

Claims

1. A gyrator circuit comprising a first and a second transconductance amplifier A and B respectively having opposite conductances, which amplifiers are arranged in parallel between a first terminal a and a second terminal b and comprises a first capacitance C₁ arranged between said first terminal a and a third terminal m, which gyrator circuit simulates an inductance L_g arranged between said second terminal b and said third terminal m and comprises means for controlling the quality factor Q of said inductance, characterized in that the first transconductance amplifier A comprises two inverting amplifier stages P₁ and P₂ arranged in series, in that the second transconductance amplifier B comprises an inverting amplifier stage P₃ and in that the means for controlling the quality factor Q comprises a first means P₅ for influencing an output conductance g₂ of the gyrator and a second means P₆ for influencing the phase shift φ

between an output current and a gyrator control voltage.

2. A circuit as claimed in claim 1, characterized in that the first means P₅ for influencing the output conductance g₂ is a variable resistance R_d coupled to the output of the gyrator between said second terminal b and said third terminal m, and in that the second means P₆ for controlling the phase shift φ

is a variable capacitance Cφ

arranged between the input of the second one P₂ of the two series-connected inverting amplifiers and said third terminal m.

3. A circuit as claimed in claim 2, characterized in that the variable resistance R_d comprises a field-effect transistor T_d which is controlled by a voltage V_d which varies in a range such that the transistor Td has a drain-source voltage near zero, and in that the variable capacitance Cφ

comprises a diode Dφ

in series with a fixed capacitance C'"'"'φ and

is controlled by a variable voltage Vφ

applied to the junction point between the diode Dφ and

the fixed capacitance C'"'"'φ

, the anode of the diode being coupled to the input of the second one P₂ of the two inverting amplifiers and the other end of the fixed capacitance C'"'"'φ

being coupled to the third terminal m.

4. A circuit as claimed in claim 3, characterized in that each inverter stage P₁, P₂ and P₃ comprises a field-effect transistor T₁, T₂, T₃, respectively, referred to as inverter transistor, whose source is coupled to said third terminal m which is at earth potential, whose drain is coupled to a d.c. supply voltage +V_DD via a load, and whose gate receives the input signal I of the inverter stage, the inverted output signal O being available on the drain of the inverter transistor, and in that the output of the inverting stage P₁ is isolated from the input of the inverting stage P₂ by a buffer stage P₄ comprising two field-effect transistors T₄ and T'"'"'₄ arranged in cascode between the earthed third terminal m and the d.c. supply voltage +V_DD, the lower transistor T'"'"'₄ being arranged as a current source, the signal from the first inverter stage being applied to the gate of the upper transistor T₄ which is biased relative to earthed terminal m by means of a resistor R₄, and the signal taken from the junction point between the transistors T₄ and T'"'"'₄ being applied to the input of the second inverter stage P₂, which input is also coupled to earthed terminal m via the variable capacitance Cφ

, the various stages being d.c. isolated from each other by means of capacitances.

5. A circuit as claimed in claim 4, characterized in that in each inverter stage P₁, P₂ and P₃ the load of the inverter transistor T₁, T₂, T₃ respectively is an active load comprising a field-effect transistor T'"'"'₁, T'"'"'₂, T'"'"'₃, respectively, whose gate is brought at a d.c. potential V_A such that V_m <

V_A <

V_DD by means of a resistor R'"'"'₁, R'"'"'₂, R'"'"'₃ respectively and is coupled to the inverter transistor of the stage via a capacitance C'"'"'₁, C'"'"'₂, C'"'"'₃, respectively, and in that the gate of the inverter transistor is biased relative to a negative potential -V_GG via a resistor R₁, R₂, R₃, respectively.

6. A circuit as claimed in claim 5, characterized in that the voltage V_A is fixed at the desired value between earth potential and the d.c. supply V_DD by a shaft in level by means of a diode D_p and a voltage drop across a resistor R_p, and in that the negative voltage -V_GG is fixed relative to earth potential by a shift in level by means of a diode D_S, said voltage -V_GG being also adjusted by a voltage drop across a resistor R₅.

7. A resonant circuit of the LC type, characterized in that it comprises an inductance L_g simulated by a gyrator circuit, said gyrator circuit comprising a first and a second transconductance amplifier A and B respectively having opposite conductances, which amplifiers are arranged in parallel between a first terminal a and a second terminal b and comprises a first capacitance C₁ arranged between said first terminal a and a third terminal m, which gyrator circuit simulates an inductance L_g arranged between said second terminal b and said third terminal m and comprises means for controlling the quality factor Q of said inductance, characterized in that the first transconductance amplifier A comprises two inverting amplifier stages P₁ and P₂ arranged in series, in that the second transconductance amplifier B comprises an inverting amplifier stage P₃ and in that the means for controlling the quality factor Q comprises a first means P₅ for influencing an output conductance g₂ of the gyrator and a second means P₆ for influencing the phase shift φ

between an output current and a gyrator control voltage; and

said resonant circuit further comprising a second capacitance C₂ connected between the second terminal b and the third terminal m.

8. A circuit as claimed in claim 7, characterized in that all the elements are monolithically integrated on a substrate of a semiconductor material comprising a compound formed from elements selected from Groups III and V.

9. A resonant filter circuit as claimed in claim 7, characterized in that it loads an amplifier P_A.

10. The circuit as claimed in claim 8 wherein said compound is gallium arsenide.

11. An oscillator, characterized in that it comprises a resonant circuit of the LC-type in which an inductance L_g is simulated by a gyrator circuit, said gyrator circuit comprising a first and a second transconductance amplifier A and B respectively having opposite conductances, which amplifiers are arranged in parallel between a first terminal a and a second terminal b and comprises a first capacitance C₁ arranged between said first terminal a and a third terminal m, which gyrator circuit simulates an inductance L_g arranged between said second terminal b and said third terminal m and comprises means for controlling the quality factor Q of said inductance, characterized in that the first transconductance amplifier A comprises two inverting amplifier stages P₁ and P₂ arranged in series, in that the second transconductance amplifier B comprises an inverting amplifier stage P₃ and in that the means for controlling the quality factor Q comprises a first means P₅ for influencing an output conductance g₂ of the gyrator and a second means P₆ for influencing the phase shift φ

between an output current and a gyrator control voltage;

said resonant circuit further comprising a second capacitance C₂ connected between the second terminal b and the third terminal m; and

the oscillation frequency is chosen by varying the capacitances C₁ and C₂.

12. An oscillator as claimed in claim 11, characterized in that the capacitances C₁ and C₂ are VARICAPS.

13. An oscillator as claimed in claim 11, characterized in that the stage P₁ includes a transistor T₁ having a gate coupled to an output S via a capacitance C₅ and to the voltage -V_GG via a resistance R₅.

14. An oscillator as claimed in claim 13, characterized in that the stage P₁ includes a transistor T'"'"'₁ having a source electrode connected to a drain electrode of transistor T₁, and the common drain-source terminal of transistors T'"'"'₁ and T₁ is coupled directly to the means P₆ and the stage P₂.