Picture processing apparatus

• US 4,812,836 A
• Filed: 12/05/1986
• Issued: 03/14/1989
• Est. Priority Date: 04/30/1985
• Status: Expired due to Fees

• Current Assignee: Fanuc Ltd (Fanuc Corporation)
• Original Assignee: Fanuc Ltd (Fanuc Corporation)
• Inventors: Kurakake, Mitsuo, Otsuka, Shoichi
• Primary Examiner(s): Yusko, Donald J.
• Assistant Examiner(s): Brier, Jeffery A.
• Application Number:
  US07/002,399
• Time in Patent Office: 830 Days
• Field of Search: 340/723, 340/724, 340/726, 340/792, 340/798, 340/799, 340/800
• US Class Current: 345/682
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 3/20 Linear translation of whole images or parts thereof, e.g. panning

Abstract

A picture processing apparatus is provided which includes a first frame memory for storing digitalized picture information and includes SAMs (serial access memories) which are capable of reading and writing parallel data with respect to the frame memory, whereby the data are transferred to a second frame memory, following an address offset, to copy the picture information. High-speed processing for translating a picture can thus be executed.

Claims

1. A picture processing apparatus for shifting picture data corresponding to a picture displayed on a display screen to a predetermined position, comprising:

(a) first frame memory means for storing one frame of picture data;

(b) second frame memory means for storing another frame of picture data;

(c) first SAM (serial access memory) means for receiving the picture data from said first frame memory means and for providing the picture data in accordance with a first shift clock;

(d) second SAM means for receiving the picture data from the first SAM means and for providing the picture data in accordance with a second shift clock;

(e) X- and Y-address counter means for designating addresses of the first and second frame memory means;

(f) register means for storing an X offset and a Y offset; and

(g) SAM controller means for providing the first shift clock in accordance with the X offset so that the first SAM means provides the picture data offset by an amount corresponding to the X offset, and providing the second shift clock in accordance with the Y offset so that the second SAM provides the picture data to an address of the second frame memory means offset by an amount corresponding to the Y offset.