Apparatus for recognizing code marks

• US 4,812,982 A
• Filed: 12/16/1986
• Issued: 03/14/1989
• Est. Priority Date: 12/16/1985
• Status: Expired due to Fees

• Current Assignee: Gunter Knapp GmbH & Company KG
• Original Assignee: Gunter Knapp GmbH & Company KG
• Inventors: PeBenhofer, Walter
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): MELNICK, STEVEN A
• Application Number:
  US06/942,343
• Time in Patent Office: 819 Days
• Field of Search: 364/555, 364/478, 235/383, 235/384, 235/385, 209/3.3, 209/546, 209/576, 198/352, 198/353, 198/354, 250/223 R, 250/578
• US Class Current: 700/226
• CPC Class Codes: B07C 3/14 using light-responsive detecting means for information carriers G06K7/14
• CPC Class Codes: G06K 7/10851 Circuits for pulse shaping, amplifying, eliminating noise signals, checking the function of the sensing device basic electronic circuitry H03

Abstract

In an apparatus for recognizing the positions, adjustable in a specific number of steps, of at least two code marks, relative to a fixed third code mark the code marks are moved relative to a read station including a specific number of code readers. The code readers are connected to a multiplexer system controlled by an address counter which interrogates the code readers sequentially and emits the results serially. The multiplexer system output is connected with a buffer memory unit to store and deliver the particular results. The output of the buffer memory unit is connected to the input of a priority encoder, the output of which is fed the binary code address of the sequentially highest input indicative of the presence of a code mark at the code readers. The priority encoder outputs are fed to two end buffer memories of which the inputs are in parallel. Two counting and memory pulse generating circuits are provided which are so connected with the address counter and the end buffer memories that when the first code reader following the passage of a first code mark recognizes the passage of a second code mark, the first end buffer memory assumes the output value from the priority encoder, and when the last code reader following the passage of a first code mark recognizes the passage of a second code mark, the second end buffer memory assumes the output value from the priority encoder.

Claims

1. An apparatus for recognizing a position of an article having a plurality of code marks by determining the relative positions of the code marks in respect to each other, comprising:

means for adjusting positions of said code marks such that the code marks are spaced a plurality of discrete distance increments from each other;

a read station including at least first and second code readers for recognizing positions of at least two of said code marks relative to a third of said code marks, said first and second code readers being spaced at a distance corresponding to a plurality of said discrete distance increments, each of said code readers generating output signals, and wherein said output signals include first signals indicative of the presence of a code mark at a code reader and second signals indicative of the absence of a code mark at a code reader;

an address counter;

a multiplexer system controlled by said address counter to sequentially interrogate said code readers and serially obtain said output signals of said code readers;

a buffer memory connected to an output of said multiplexer system to store said output signals at addresses corresponding to the positions of the code readers;

a priority encoder connected to an output of said buffer memory, said priority encoder generating output signals corresponding to an address of the serially highest of said first signals indicative of the presence of a code mark;

first and second end buffer memories connected to the output of said priority encoder, said end buffer memories having parallel inputs;

wherein said first and second end buffer memories are controlled by first and second pulse generators so that the first end buffer memory receives said priority encoder output signals in response to output by said first code reader of said first signal indicative of the presence of a code mark at said first code reader, and so that the second end buffer memory receives the priority encoder output signals in response to output by said first and second code readers of subsequent first signals indicative of the presence of a code mark at said second code reader, whereby the priority encoder output signals received by said second end buffer memory in response to the subsequent first signal indicative of the presence of a code mark at said second code reader correspond to the relative positions of the code marks.

2. An apparatus as claimed in claim 1, wherein:

said code readers comprise an emitter element and an associated detector element;

said multiplexer system comprises first and second multiplexers having parallel address conductors connected to the outputs of said detector elements of said code readers so as to sequentially interrogate said detectors after a time delay;

said first and second multiplexers include a decoder having address inputs parallel to the outputs of said multiplexers and outputs to drive said emitter elements so that, as said first multiplexer interrogates said detector elements, associated emitter elements are driven and the second multiplexer is followed by

a delay circuit connected to the output of said second multiplexer to introduce a delay time between the output signals of the first and second multiplexers;

a subtractor to receive the output signals of said first multiplexer and said delay circuit so that said subtractor outputs a signal corresponding to the value of an emitter element less the value, measured at a lead time, of the same detector element for an emitter element that is not driven.

3. An apparatus as claimed in claim 1, further comprising means for generating an output signal only when two code marks are present at said read station;

and

AND gates connected to receive the output of said output signal generating means and to supply an input to said first and second pulse generators.

4. The apparatus as claimed in claim 3, wherein said AND gate also receives a second sequential output of said address counter.

5. An apparatus as claimed in claim 3, wherein said means for generating an output signal further comprises:

a counter connected to the output of said multiplexer system to count switching transactions in a single multiplexer scanning cycle during which the multiplexer interrogates each of the code readers; and

a counter buffer memory connected to said counter and to an output of said address counter so as to be reset if an output from said counter corresponds to the output from said address counter, wherein said switching transactions correspond to outputs by said code readers which are indicative of the presence of a code mark at the corresponding code reader.

6. An apparatus as defined in claim 5, wherein:

housings for said code readers of said read station comprise reflecting light barriers having perpendicularly mounted light emitters and light detectors;

said code reader housings further comprising cylindrical lenses mounted as close as possible to the said light emitters and light detectors and aligned along a direction of advancement of said code marks, said cylindrical lenses mounted directly next to each other to form said read station.

7. An apparatus as claimed in claim 3, wherein said multiplexer system interrogates each code reader several times while a particular code mark moves past each code reader.

8. An apparatus as claimed in claim 7, further comprising a protective circuit for generating an output signal to release said pulse generators circuits in response to at least one of said code readers recognizing a code mark over a plurality of interrogation cycles.

9. An apparatus as claimed in claim 8, wherein said code readers are capable of generating reset pulses, and wherein said protective circuit comprises first and second counters having means for, during each interrogation cycle, counting up to a predetermined level determined by said address counter and being frozen in this state until receipt of a reset pulse generated by either said first or second code reader.

10. An apparatus as claimed in claim 8, further comprising:

a delay circuit connected to the output of said multiplexer system, said delay circuit having a fixed time constant;

a monitoring circuit connected to the output of said delay circuit for supplying a signal to said end buffer memories so that said end buffer memories are reset after a time interval exceeding said time constant.

11. An apparatus as claimed in claim 10, wherein said monitoring circuit comprises a retriggering monostable multivibrator.