Digital audio memory system

• US 4,813,014 A
• Filed: 04/14/1986
• Issued: 03/14/1989
• Est. Priority Date: 04/14/1986
• Status: Expired due to Fees

• Current Assignee: PHI Technologies Incorporated
• Original Assignee: PHI Technologies Incorporated
• Inventors: DeBell, Lawrence R.
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): Gossage, Glenn A.
• Application Number:
  US06/851,453
• Time in Patent Office: 1,065 Days
• Field of Search: 365/45, 365/189, 365/52, 365/230, 360/32, 364/200 MS File, 364/900 MS File, 379/88, 375/27
• US Class Current: 365/45
• CPC Class Codes: G11C 2207/16 Solid state audio deprecated, only for historical reasons, G06F3/16, G11B
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A method and apparatus for rapid access digital storage and playback of audio information that consists of a large array of solid state random access memory devices connected in a basic multi-group, multi-card, multi-unit configuration that is addressable in one second increments for a selected duration. Storage or playback with requisite signal conversion may be effected by inputting real time decimal address indications to select a designated time and duration of the total memory capacity.

Claims

1. Apparatus for storage and retrieval of audible information, comprising:

control means that includes, timing means generating a basic timing pulse at a selected frequency, counter means responsive to said timing pulses to generate a random access memory address code output, and a microprocessor receiving code input indicating information memory location in storage and outputting at least a memory group address code output;

memory card means that includes plural memory groups of random access memory means arrayed in parallel wherein each of said memory groups consists of an equal number of said random access memory means, means connecting said random access memory address code output to control ports of each of said random access memory means, decoder means receiving said memory group address code output to enable a selected one of said plural memory groups of random access memory means, and input/output means selectively connected to respective random access memory means of a selected memory group; and

audio means including first converter means for digitizing audio for input to said input/output means for storage at a selected random access memory location, and second converter means for receiving digital data output form a selected random access memory location and outputting analog audio signal for audible output.

2. Apparatus as set forth in claim 1 wherein:

there are four random access memory means in each group.

3. Apparatus as set forth in claim 1 wherein said audio means further comprises:

analyzer/synthesizer means for effecting adaptive differential pulse code modulation.

4. Apparatus as set forth in claim 1 which further includes:

keypad selection means manually operable to output a binary coded decimal output indicative of information memory location for input to the microprocessor; and

display means corresponding to said information memory location.

5. Apparatus as set forth in claim 4 wherein:

said numbers equate to real time designation of the total available time in the memory card means.

6. Apparatus as set forth in claim 1 which further includes:

at least one additional memory card means connected to said control means in like manner;

a first card address code output from said microprocessor indicating a selected one of the memory card means; and

decoder means on each memory card means receiving said card address code output to provide a card enable output to enable the selected memory card means.

7. Apparatus as set forth in claim 6 which further includes:

a plurality of slave units with each such unit consisting of plural memory card means connected to said control means in like manner;

a second unit address code output from said microprocessor indicating a selected one of the slave units; and

second decoder means on each memory card means receiving said second unit address code output to provide a unit enable output to enable the selected slave unit.

8. Apparatus as set forth in claim 7 which further includes:

keypad selection means manually operable to output a binary coded decimal output indicative of information memory location for input to the microprocessor; and

display means corresponding to said information memory location.

9. Apparatus as set forth in claim 8 wherein:

said numbers equate to real time designation of the total available time in the memory card means.

10. Apparatus as set forth in claim 7 wherein:

there are as many as ten groups of random access memory on each memory card means, and as many as ten random access memory card means on each unit, and as many as eight units responsive to said control means.

11. Apparatus as set forth in claim 10 wherein:

there are four random access memory means in each group.

12. Apparatus as set forth in claim 1 wherein the control means counter means further comprises:

a binary counter counting down said timing pulse to provide a clock pulse at a selected rate;

a row address counter responsive to said clock pulse to generate row address output;

a column address counter that is clocked each time the row address counter completes a row address cycle to generate a column address output; and

tri-state buffer means controlled at a selected switching rate to alternately connect the row address output and the column address output to a random access memory address buss to said memory card means.

13. Apparatus as set forth in claim 12 wherein:

said clock pulse rate is 6553 Hertz.

14. Apparatus as set forth in claim 12 which further includes:

a dividing counter counting a clock pulse input and generating a refresh pulse of selected pulse width;

a refresh counter response to said timing pulses to generate an alternate source of second row address output pulses; and

tri-state buffer means controlled during said refresh pulse to switch said second row address output pulses to said random access memory address buss at a selected multiple of said clock pulse rate.

15. Apparatus as set forth in claim 14 wherein:

said clock pulse rate is 6553 Hertz and said basic timing pulse has a frequency of 1.677568 Megahertz.

16. Apparatus as set forth in claim 12 which further includes:

gate means responsive to said timing pulse and said refresh pulse to generate a periodic row address strobe for input to said random access memory means.

17. Apparatus as set forth in claim 16 which further includes:

gate means responsive to said clock pulse and said refresh pulse to generate a periodic column address strobe input to the memory card means to enable said memory group address code for input to said decoder means.

18. A method for recording and playback of selected segments of audio information, comprising:

defining a memory bank by connecting a plurality of similar random access memory devices as at least one unit having plural memory cards, each memory card consisting of a plurality of memory groups with each group having a preset number of memory devices with addressable locations;

addressing said memory bank in real time in one second increments wherein a first decimal input addresses a selected unit in the memory bank, a second decimal input addresses a selected memory card in the unit, a third decimal input addresses a selected group on the card, and a fourth decimal input addresses a selected location in the group;

enabling selective storage and playback of data from the addressed location of the memory bank; and

effecting selective analog/digital and digital/analog conversion of data for respective storage and playback functions.

19. A method as set forth in claim 18 wherein:

a storage access time window may be defined by first selecting a start address of first, second, third and fourth decimal inputs and subsequently entering a stop address of first, second, third and fourth decimal inputs.

20. A method as set forth in claim 18 wherein:

the memory bank may include up to 10 seconds storage per group, up to 10 groups per card, up to 10 cards per unit, and up to 8 units per bank to provide a total of up to 8000 seconds of selectively addressable digital storage.

21. A method as set forth in claim 18 wherein:

each group consists of a parallel array of memory devices that output four bit binary data under a common clock control.

22. A method as set forth in claim 21 wherein:

the memory bank may include up to 10 seconds storage per group, up to 10 groups per card, up to 10 cards per unit, and up to 8 units per bank to provide a total of up to 8000 seconds of selectively addressable digital storage.