Video display control system having improved storage of alphanumeric and graphic display data

• US 4,814,756 A
• Filed: 01/28/1987
• Issued: 03/21/1989
• Est. Priority Date: 12/12/1980
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chauvel, Gerard
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US07/009,578
• Time in Patent Office: 783 Days
• Field of Search: 340/721, 340/726, 340/724, 340/747
• US Class Current: 345/565
• CPC Class Codes: G06F 2205/123 Contention resolution, i.e. resolving conflicts between simultaneous read and write operations
• CPC Class Codes: G06F 5/12 Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
• CPC Class Codes: G06F 5/14 for overflow or underflow handling, e.g. full or empty flags
• CPC Class Codes: G09G 5/343 for systems having a character code-mapped display memory
• CPC Class Codes: G09G 5/40 characterised by the way in which both a pattern determined by character code and another pattern are displayed simultaneously, or either pattern is displayed selectively, e.g. with character code memory and APA, i.e. all-points-addressable, memory
• CPC Class Codes: H04N 7/0255 Display systems therefor
• CPC Class Codes: H04N 7/035 Circuits for the digital non-picture data signal, e.g. for slicing of the data signal, for regeneration of the data-clock signal, for error detection or correction of the data signal

Abstract

A system for displaying alphanumeric and graphic information on a raster scanned display device, for example, in a teletext system, includes a memory which is updated to change the display. Dynamic changes in the displayed image are provided by assigning a base address to each of one or more zones in the memory and altering the base addresses as required under local or remote control. Alphanumeric and graphic data may be combined on a single displayed page by means of identification data associated with each row or line of data to be displayed. The required capacity of the memory associated with the display device is substantially reduced by assigning a control code to data which is to be repetitively displayed, for example, spaces at the end of a line or fields of uniform color. Selected elements are thus displayed a predetermined number of times without the need for a corresponding number of memory locations. Incoming data may be sotred in a buffer memory at a greater rate than can be processed by the present system by means of a control circuit which inhibits the inputting of data for a period of time when there is a risk of overwriting or erasure of previously stored data.

Claims

1. A display control system comprising:

a first memory means including a plurality of address registers for storing therein page start addresses;

a second memory means including a plurality of page memories, each page memory starting at an address corresponding to the page start address stored in a corresponding address register of said first memory means and having stored therein display data for controlling a page of display, said display data stored in memory zones corresponding to video lines in one of a predetermined set of display modes, said display modes comprising a character mode and a graphics mode, wherein said character mode display data is stored in the form of address words, and wherein said graphics mode display data is stored in the form of a dot pattern, said page memories having further stored therein display mode data which identified the display mode corresponding to individual video lines;

a data processor means connected to said first and second memory means for recalling display data from page memories of said second memory means in accordance with page start addresses stored in said first memory means, said display data thereby recalled in the order of display;

character generator means, coupled to said data processor means and to said second memory means, for storing display data in the form of dot pattern character representations representing a plurality of alpha-numeric characters in locations addressable according to the address words recalled by said data processor means in the character mode; and

a video control means connected to said second memory means of receiving said recalled dot pattern graphic display data in the graphics mode, and connected to said character generator means for receiving said dot pattern character representations corresponding to address words recalled in the character mode, said video display generator for generating video signals in accordance with said received dot pattern character representations and said dot pattern graphic display data.

2. The display control system of claim 1, further comprising:

a video display means connected to said video control means for producing a visually perceivable image corresponding to said video signals.

3. The display control system of claim 1, wherein:

each of said memory zones corresponding to a video line includes display mode data stored at the end thereof, said display mode data identifying the display mode of the next succeeding video line.

4. The display control system of claim 1, wherein said video control means further includes means for selectively displaying alphanumeric and graphic elements on a single displayed page of data comprising:

decoder means coupled to said character generator means, to said second memory means and to said video display means for providing the received dot pattern character representations and the received dot pattern graphic display data to said video display means at the raster scanning rate; and

mode control means coupled to said second memory means, said character generator means and said decoder means for interpreting display mode data stored in said second memory means which identifies the next successive data to be displayed as either a row of alphanumeric characters or a line or graphic elements, wherein said mode control means provides a signal to said decoder means enabling the display of data in the identified display mode.

5. The display control system of claim 4, wherein said mode control means comprises:

register means responsive to a margin signal corresponding to the end of the display zone of said video display means, wherein said register means enables said decoder means to display said dot pattern graphic display data received directly from said second memory means, and said dot pattern character representations received from said character generator means corresponding to said address words recalled from said second memory means.

6. The display control system of claim 5, further including means for displaying repetitive alphanumeric or graphic data comprising:

repeat control means coupled to said second memory means, said decoder means, said character generator means and said data processor means for interpreting a repetition code in said second memory means associated with the data to be repetitively displayed, wherein upon detecting said repetition code said repeat control means inhibits the reading of said second memory means while causing said data to be displayed a predetermined number of times.

7. The display control system of claim 4, further comprising:

a buffer memory means for inputting display data into said second memory means at a rate exceeding the data reading rate of said data processor means;

first address register means for successively addressing memory locations of said buffer memory means by incrementing at the reading rate of said data processor means;

second address register means for successively addressing memory locations of said buffer memory means by incrementing at said inputting rate;

buffer address control means connected to said first and second address register means for generating an inhibit signal upon the equality of addresses stored in said first and second address register means, wherein said buffer address control means inhibit signal inhibits the inputting of display data into said buffer memory means until said data processor means has completely read the display data stored in said buffer memory.

8. The display control system of claim 7, wherein said buffer address control means comprises:

comparator means coupled to said first and said second address register means for comparing the contents thereof and generating an output signal when an equality is detected;

logic gate means coupled to said comparator means output for inhibiting the incrementing of said second address register means when said comparator means output signal is present; and

multiplexer means coupled to said first and said second address register means and to said second memory means for alternately enabling the addressing of said second memory means by said data processor means and said inputted display data.

9. A method of displaying graphic and character data by a display control system which displays data on a video display of the raster scan type, said data arranged in a predetermined number of lines corresponding to line sweeps of said video display, said method comprising the steps of:

storing in a page memory the data to be displayed on said video display, said data arranged according to lines of said display and comprising;

for each line of character data, address values corresponding to the addresses of dot matrix character patterns stored in a character generator;

for each line of graphics elements, a dot pattern; and

for each line of either character data or graphics elements, and identification code indicating whether the next data to be displayed comprises character data or graphic elements;

determining from said identification code if the mode of display for each line sweep is of character or graphics type; and

if said mode of display for a given line sweep is of character type,

accessing said page memory to obtain the locations in said character generator containing the alphanumeric characters to be displayed; and

if said mode of display for a given line sweep is of graphics type,

accessing said page memory to obtain the dot pattern for forming the graphic elements to be displayed.

10. The method of claim 9, further including the steps of:

storing a repetition code and a repetition value in said page memory associated with a selected stored element to be repeatedly displayed on said display device, said stored element being a character generator address in character mode and a dot pattern in graphics mode;

inhibiting the accessing of said page memory a number of times corresponding to said repetition value upon detection of said repetition code;

displaying an image corresponding to said selected stored element said number of times; and

thereafter enabling the continued accessing of said page memory.

11. The method according to claim 9, further including a method for transferring data between a first system and a second system, wherein said second system has a greater data processing rate than said first system, comprising the steps of:

storing the data supplied by said second system in a buffer memory under control of a first address register capable of successively addressing all of the memory locations in said buffer memory at the data processing rate of said second system;

successively retrieving said stored data under control of a second address register capable of successively addressing all of the memory locations in said buffer memory at the data processing rate of said first system;

comparing the contents of said first and said second address registers and generating a signal when an equality is detected therebetween; and

inhibiting the addressing of said buffer memory by said first address register upon the occurrence of said comparison signal, thereby inhibiting the transfer of data from said second system and preventing the overwriting in said buffer memory of data not yet retrieved by said first system.

12. The method of claim 11, further including the steps of:

comparing the contents of said first address register with the address of the first location in said buffer memory and generating a second signal upon the equality thereof;

comparing the contents of said second address register with the address of the first location in said buffer memory and generating a third signal upon the equality thereof; and

inhibiting the addressing of said buffer memory said first address register only if said first signal occurs after the occurrence of said second signal and before the occurrence of said third signal.