High transconductance complementary (Al,Ga)As/gas heterostructure insulated gate field-effect transistor

• US 4,814,851 A
• Filed: 04/28/1988
• Issued: 03/21/1989
• Est. Priority Date: 06/21/1985
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Abrokwah, Jonathan K., Shur, Michael S., Cirillo, Nicholas C. Jr., Tufte, Obert N.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Prenty, Mark
• Application Number:
  US07/188,069
• Time in Patent Office: 327 Days
• Field of Search: 357/42, 357/16, 357/22 A, 357/22 MD, 357/67, 357/15
• US Class Current: 257/192
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 29/432 Heterojunction gate for field effect devices
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

A complementary (Al,Ga)As/GaAs heterostructure insulated gate field-effect transistor (HIGFET) approach is described in which both the n-channel and p-channel transistors utilize a two-dimensional electron (hole) gas in undoped high mobility channels to form planar, complementary GaAs-based integrated circuits.

Claims

1. A complementary, planar heterostructure IC in which both the n-channel and p-channel transistors utilize a 2D electron (hole) gas in an undoped high mobility channel to form CMOS-like IC'"'"'s, the complementary, planar IC structure comprising:

semi-insulating compound semiconductor substrate means having a flat major surface;

a first epitaxially grown layer of a first insulating III-V compound semiconductor over said surface, said insulating compound semiconductor layer having high mobility and having a first bandgap;

a second epitaxially grown layer of a second insulating III-V compound semiconductor, which second insulating compound semiconductor has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands, said second layer having a planar surface;

first and second metal gate electrodes deposited directly on said surface of said second epitaxial layer, said epitaxial layers under said metal gate electrodes being undoped;

a n⁺ source and a n⁺ drain region defined by selective donor ion implantation in said epitaxial grown layer structure next to said first gate electrode;

a p⁺ source and p⁺ drain region defined by selective acceptor ion implantation in said epitaxial grown layer structure next to said second gate electrode;

first and second n-ohmic contacts directly on said second layer surface and alloyed to said n-source and n-drain regions, respectively; and

,

third and fourth p-ohmic contacts directly on said second layer surface and alloyed to said p-source and p-drain regions, respectively.

2. The structure according to claim 1 in which the compound semiconductor substrate means is of semi-insulating GaAs.

3. The structure according to claim 2 in which the first epitaxially grown layer is undoped insulating-GaAs, and the second epitaxially grown layer is insulating (Al,Ga)As.

4. The structure according to claim 3 in which said metal gate electrodes are WSi.

5. The structure according to claim 3 in which said second donor ion implantation is of silicon ions.

6. The structure according to claim 3 in which said selective acceptor ion implantation is of Mg or Be ions.

7. The structure according to claim 3 in which said n-ohmic contacts are AuGeNi-based.

8. The structure according to claim 3 in which said p-ohmic contacts are AuZn-based.

9. A planar complementary GaAs based heterostructure integrated circuit structure having complementary self-aligned gate (Al,Ga)As/GaAs heterostructure devices with an insulating (Al,Ga)As (SAG) gate structure to form CMOS-like GaAs IC'"'"'s the planar complementary IC structure comprising:

semi-insulating GaAs substrate means having a flat major surface;

a MBE grown layer of insulating-GaAs over said surface;

a MBE grown layer of insulating (Al,Ga)As over said layer of i-GaAs said layer of (Al,Ga)As having a planar surface;

first and second metal gate electrodes deposited directly on said surface of said i-(Al,Ga)As layer, said epitaxial layers under said metal gate electrodes being undoped;

a n⁺ source and a n⁺ drain defined by selective donor ion implantation in said MBE structure next to said first gate electrode;

a p⁺ source and a p⁺ drain region defined by selective acceptor ion implantation in said MBE structure next to said second gate electrode;

first and second n-ohmic contacts directly on said (Al,Ga)As planar surface and alloyed to said n-source and n-drain regions, respectivley; and

,

third and fourth p-ohmic contacts directly on said (Al,Ga)As planar surface and alloyed to said p-source and p-drain regions, respectively.

10. The structure according to claim 9 in which said metal used in said gate electrode is WSi.

11. The structure according to claim 9 in which said selective donor ion implantation is of silicon ions.

12. The structure according to claim 9 in which said selective acceptor ion implantation is of Mg or Be ions.

13. The structure according to claim 9 in which said n-ohmic contacts are AuGeNi-based.

14. The structure according to claim 9 in which said p-ohmic contacts are AuZn-based.

15. A planar complementary GaAs based heterostructure integrated circuit structure comprising:

semi-insulating GaAs substrate means having a flat major surface;

planar epitaxial grown III-V insulating layers over said flat major surface including at least a first grown i-GaAs layer and a final grown i-Al_x Ga_1-x As layer, said final grown layer having a planar surface;

first and second metal gate electrodes deposited directly on said planar surface of the final layer of said insulating layers, said epitaxial grown insulating layers under said metal gate electrodes being undoped;

a n⁺ source a n⁺ drain region in said epitaxial grown layer structure defined by selective donor ion implantation into said structure next to said first gate electrode;

a p⁺ source a p⁺ drain region in said structure defined by selective acceptor ion implantation into said epitaxial grown layer structure next to said second gate electrode;

first and second n-ohmic contacts directly on said final layer surface and alloyed to said n-source and n-drain regions, respectively; and

,

third and fourth p-ohmic contacts directly on said final layer surface and alloyed to said p-source and p-drain regions, respectively.

16. The structure according to claim 15 in which x, the composition of the (Al,Ga)As layer can be variable throughout the layer.

17. The structure according to claim 15 in which the composition x, of the i-Al_x Ga_1-x As layer, is 1 (i.e. AlAs).

18. A complementary, planar heterostructure IC in which both the n-channel and p-channel transistors utilize a 2D electron (hole) gas in an undoped high mobility channel to form CMOS-like IC'"'"'s, the complementary, planar IC structure comprising:

semi-insulating compound semiconductor substrate means having a flat major surface;

planar epitaxial grown undoped III-V insulating layers over said flat major surface including a first epitaxially grown layer of a first undoped compound semiconductor over said surface, said undoped compound semiconductor layer having high mobility and having a first bandgap, and a second epitaxially grown layer of a second undoped compound semiconductor, which second undoped compound semiconductor has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands said second layer having a planar surface;

first and second metal gate electrodes deposited directly on said surface of said second undoped epitaxial layers, said epitaxial grown undoped insulating layers under said metal gate electrodes being undoped whereby there is no doped layers beneath said metal gate electrodes;

a n⁺ source a n⁺ drain region defined by selective donor ion implantation in said epitaxial grown layer structure next to said first gate electrode;

a p⁺ source and a p⁺ drain region defined by selective acceptor ion implantation in said epitaxial grown layer structure next to said second gate electrode;

first and second n-ohmic contacts directly on said second layer surface and alloyed to said n-source and n-drain regions, respectively; and

,

third and fourth p-ohmic contact directly on said second layer surface and alloyed to said p-source and p-drain regions, respectively.

19. The complementary, planar heterostructure IC according to claim 18 in which said first undoped compound semiconductor is i-GaAs and said second undoped compound semiconductor is i-AlGaAs.