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Structured design method for high density standard cell and macrocell layout of VLSI chips

  • US 4,815,003 A
  • Filed: 06/19/1987
  • Issued: 03/21/1989
  • Est. Priority Date: 06/19/1987
  • Status: Expired due to Fees
First Claim
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1. A method for laying out an assemblage of intermixed fixed size and shape rectangular macrocells and amorphous clusters of standard cell logic elements in a target region, comprising the steps of:

  • performing a first affinity factor evaluation of first affinity factors of all possible pairs of logic elements;

    generating low-order standard cell subdomains consisting of logic element pairs having the most positive first affinity factors;

    performing a second affinity factor evaluation of the affinity factors of all possible pair combinations of standard cell subdomains and logic elements;

    generating higher-order standard cell subdomains, consisting of pairings of one of (a) standard cell subdomains with other standard cell subdomains, (b) standard cell subdomains with logic elements, and (c) logic elements with other logic elements, which pairings include only sets having identical second affinity factors;

    iteratively repeating said performing a second affinity factor evaluation and generating higher-order steps to generate standard cell domains until combining any pair results in a second affinity factor more negative than zero;

    performing a third affinity factor evaluation of the affinity factors of all possible pairs of macrocells and standard cell domains;

    pairing those of said macrocells and standard cell domains having the most positive value of said third affinity factor to form superdomains;

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