Virtual memory image controller for multi-windowing

• US 4,815,010 A
• Filed: 05/13/1986
• Issued: 03/21/1989
• Est. Priority Date: 05/15/1985
• Status: Expired due to Fees

• Current Assignee: Ciaran O'Donnell
• Original Assignee: Ciaran O'Donnell
• Inventors: O'Donnell, Ciaran
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): LaCasse, Randy W.
• Application Number:
  US06/862,780
• Time in Patent Office: 1,043 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/518, 364/521, 364/523, 358/160, 340/723, 340/724, 340/726, 340/734, 340/747, 340/721
• US Class Current: 345/531
• CPC Class Codes: G09G 5/14 Display of multiple viewports

Abstract

A virtual memory image controller for multi-windowing, comprises a bidimensional image memory organized in N elementary blocks, N being an integer, the blocks being of fixed size and rectangular, a random access read/write memory containing a sequence of N pointers, each pointer noting the beginning address of a block in the image memory, a video signal generator delivering a video signal corresponding to the contents of n blocks of the image memory, NSN, for the display on a screen of the image composed of n blocks organized in amatrix, the blocks be ing addressed by the video generator via a table of indirection, an interface for read/write accesses to the image memory, the accesses being made via the indirection table, the controller comprising also a data bus, an address bus, a command bus, and a sequencer.

Claims

1. Virtual memory controller comprising:

a bidimensional image memory (4) organized in N elementary blocks, N being an integer, the said blocks being of fixed size and rectangular,

an indirection table (6) constituted by a random access read/write memory containing a sequence of N pointers, each pointer indicating the beginning address of a block in the image memory,

a divider address,

a video generator (10) delivering a video signal corresponding to the contents of n blocks of the image memory, where n≦

N, for the display on a screen of an image composed of the n blocks organized in a matrix, the addressing of said blocks being made by the video generator via the indirection table,

an interface (12) to access in read/write to the image memory and the indirection table, the addressing of the memory being made via the divider address and via the indirection table,

an address bus which permits the addressing by the video generator via the divider address and via the indirection table of the image memory,

an address bus which permits the addressing by the interface via the divider address and via the indirection table of the image memory, and

a bidirectional data bus which is common to the interface, the video generator and the image memory.

2. The controller according to claim 1, characterized in that said indirection table includes n initial pointers in said read/write memory and the n blocks displayed on the screen are those indicated by the n initial pointers of the indirection table.

3. The controller according to claim 2, characterized in that it also comprises address decomposing means (26) placed between, on one hand, the video generator (10) and the interface (12) and, on the other hand, the indirection table (6), said means receiving the addresses delivered by said video generator and said interface and decomposing each address into an upper part representing the beginning of a block in the image memory and a lower part representing an index designating a word in said block, the upper part of the address being received by the indirection table and the lower part by the image memory.

4. The controller according to claim 3, characterized in that said address decomposing means (26) comprises a first line address register (28) and a first column address register (30) receiving the address delivered by the video generator, a second line address register (32) and a second column address register (34) receiving the addresses delivered by said interface, and means (40, 42, 44, 46) for concatenating the upper address parts delivered by a line address register and a column address register, the address resulting from the concatenation of the upper address parts being applied to the indirection table and the address resulting from the concatenation of the lower address parts being applied to the image memory.

5. The controller according to claim 1 in which the interface (12) receives a one-dimensional address signal from the processor characterized in that the interface (12) comprises in serial a conditional permutation means and a memory management unit, said permutation means being commanded to permute the bits in order to render said address bidimensional when it is destined for the image memory.

6. The controller according to claim 1 in which the interface (12) receives an uni-dimensional address signal from the processor characterized in that the interface (12) comprises a memory management unit, the said interface delivering on the address bus a bidimensional address by permutation of address lines.