Dynamic memory address system for I/O devices

• US 4,815,034 A
• Filed: 03/18/1981
• Issued: 03/21/1989
• Est. Priority Date: 03/18/1981
• Status: Expired due to Fees

• Current Assignee: Timothy I. Mackey
• Original Assignee: Timothy I. Mackey
• Inventors: Mackey, Timothy I.
• Primary Examiner(s): Heckler, Thomas M.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US06/245,145
• Time in Patent Office: 2,925 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/64
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

Individual pieces of digital equipment such as I/O units are provided each with a connect circuit which includes a ROM containing an otherwise incomplete but device-specific, dedicated service program; and each such program portion completes a likewise incomplete program contained in a processor so that this processor can serve as a time-shared controller for each I/O unit. The system includes a common bus, and particular features relate to process inclusion of all ROM'"'"'s in a common memory continuum.

Claims

1. A digital data system provided for recieving and/or issuing data, comprising:

a processor;

a bus which includes a data bus, address bus, and control lines connected to the processor;

a basic memory, including at least one RAM and one ROM connected to said bus and containing an operating system;

at least two I/O units connected to said bus, respectively constituting a source and/or a destination for data to be set into, transmitted by, and/or received from said data bus; and

a supplemental memory included in each of the I/O units and including a ROM portion as well as containing device-specific program portions to be executed by the processor so that the processor in conjunction with said basic and supplemental memories functions as a controller for said unit, whereby said bus operatively couples the supplementary memory to the processor so that the processor transmits addresses for accessing the ROM portion containing the device specific program portions, via said bus and receives from the ROM portion as accessed, also via said bus, instructions for execution for purposes of controlling the respective I/O unit including data transfer to or from the unit via the bus.

2. A system as in claim 1, and being connected to a host computer via said bus and said interface.

3. A system as in claim 1, the bus including interface means for connection to a host computer.

4. A system as in claim 1, the supplemental memory including also a RAM portion.

11. A data system including two of the systems as set forth in claim 1 and communicating via an interface interconnecting the respective buses.

12. A system as in claim 1, each of said units including register means connected to the data lines for receiving therefrom and holding a variable block address, further having a plurality of output lines;

the respective ROM in each of said units having address inputs connected to others of said address lines and being enabled in response to an output of said first decoder means; and

an input circuit for the register means in each unit and being connected to the data bus to receive therefrom a block address for storage in the register means pursuant to said enabling operation in response to said access code.

13. A digital data system as in claim 1 where each I/O unit includes register means connected to the data bus for receiving therefrom and holding a variable block address, further having a plurality of output lines;

first block address decoder means connected to said output lines and to some lines of said address bus for providing an output when said various address lines hold the block address as stored in said register means;

said ROM portion holding a portion of a service program for the respective I/O device having address inputs connected to other lines of said address bus and being enabled in response to an output of said first decoder means; and

second decoder means connected to particular lines of one of the buses to be responsive to an access code and providing an enabling operation for said register means;

the register means as connected to said data receiving therefrom the block address address for storage in the register means pursuant to said enabling operation in response to said access code.

14. A digital data system as in claim 1 wherein each I/O unit includes:

a register means for holding an address portion;

a decoder coupled to an output of said register and further connected to portion of said address bus for providing to the ROM a ROM-enabling signal upon response by said decodere;

a remainder of the address bus being connected to the ROM for accessing of memory locations therein and for setting the content of an accessed ROM location into said data bus, including at least one instruction pertaining to said service program; and

circuit means connected to said bus for receiving therefrom instruction execution signals following the setting of said instruction from the ROM into said data bus, the instruction execution being used in the operation of said I/O device for purposes of a data transfer across said bus.

5. In a digital data system which includes a bus, a processor, and a memory, both connected to the bus, the system further including at least one input/output device to be serviced by the processor, the improvement comprising:

the memory storing an incomplete program portion for servicing said input/output device; and

a connection circuit connecting the bus to the device and constituting a portion of the device and including a ROM portion containing a remaining portion of a service program for said device so that said incomplete portion and said remaining portion together constitute a complete service program for said one device, said connection circuit including means for connecting said ROM to said bus, so tha the bus couples the ROM portion to said processor enabling said processor to accesss said service program portion in said ROM portion.

8. In a circuit as in claim 5, 6 or 7 and including additional circuit means holding a digital representation of a capacity of said ROM, the content of the circuit means being supplied to said bus in response to particular signals arriving as control signals on said bus.

9. In a circuit as in claim 5, 6, or 7 and including additional register means having one side connected to said ROM for temporarily storing data or buffering from the ROM and having its other side connected to a data portion of said bus.

10. In a circuit as in claim 9 and including an internal bus connected to I/O for the feeding data to, or receiving data from, said internal bus, the internal bus also connecting an output of said ROM to one side of said additional register means, either side of said additional register means being capable of inputting and outputting.

6. A circuit for connection to a bus which includes data lines, memory address lines, and control lines, comprising:

register means connected to the data lines for receiving therefrom and holding a variable block address, further having a plurality of output lines;

first block address decoder means connected to said output lines and to some of said address lines for providing an output when said various address lines hold the block address as stored in said register means;

A ROM which holds portions of a service program for an I/O device and having address inputs connected to others of said address lines and being enabled in response to an output of said first decoder means; and

second decoder means connected to particular lines of the bus to be responsive to an access code and providing an enabling operation for said register means;

the register means as connected to said data lines receiving therefrom the block address for storage in the register means pursuant to said enabling operation in response to said access code.

7. An interface circuit for connection to a bus and including a ROM which contains a portion of a service program for an I/O device;

a register means for holding an address portion;

a decoder coupled to an output of said register and further connected to an address portion of the bus for providing to the ROM a ROM-enabling signal upon response by said decoder;

a remainder of the address bus being connected to the ROM for accessing of memory locations therein and for setting the content of an accessed ROM location into a data portion of said bus, including at least one instruction pertaining to said service program; and

circuit means connected to said bus for receiving therefrom instruction execution signals following the setting of said instruction from the ROM into said data bus portion, the instruction execution being used in the operation of said I/O device for purposes of a data transfer across said bus.