BPSK demodulator and FM receiver for digital data pagers

• US 4,816,769 A
• Filed: 01/16/1987
• Issued: 03/28/1989
• Est. Priority Date: 06/21/1985
• Status: Expired due to Fees

• Current Assignee: Astec International Limited (Emerson Electric Company)
• Original Assignee: John Y. Ma, Louis H. Jandrell
• Inventors: Jandrell, Louis H., Ma, John Y.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): MIS, DAVID C
• Application Number:
  US07/003,843
• Time in Patent Office: 802 Days
• Field of Search: 329/50, 329/110, 329/112, 329/122, 329/124, 329/126, 329/134, 375/81-84, 375/87, 375/99, 375/102-104, 375/120, 455/214, 455/337, 455/161, 455/192, 455/208
• US Class Current: 329/315
• CPC Class Codes: H03D 1/2254 and a phase locked loop
• CPC Class Codes: H03D 2200/0031 PLL circuits with quadrature locking, e.g. a Costas loop
• CPC Class Codes: H04B 1/16 Circuits

Abstract

An FM receiver for the reception of digital data modulated on a Subsidiary Communication Authorization (SCA) subcarrier is provided with automatic tuning capability and a coherent demodulator for minimizing noise, distortion and interference. The FM receiver is tuned automatically to minimize the measured amplitude of noise and distortion at the high frequency end of the spectrum of the FM demodulator output, above the frequencies of the SCA signal. The SCA signal is tuned by a heterodyne circuit including a balanced modulator, a voltage-controlled oscillator (VCO), and a bandpass filter. The VCO is automatically tuned to maximize the measured amplitude of the SCA signal selected by the bandpass filter. For coherent detection of BPSK (Binary-Phase-Shift-Keying), the coherent demodulator is preferably and kind of data-aided Costas loop in which digital logic circuits perform phase shifting, phase detecting, a multiplying functions. The feedback of the phase error signal is preferably inhibited whenever the signal-to-noise ratio falls below the level which ensures phase-lock, for example, by inhibiting feedback whenever the amplitude of the filtered in-phase signal in the Costas loop fails to exceed a predetermined threshold level. Preferably the phase error signal is fed back through an integrating low-pass filter to control the VCO of the heterodyne circuit, and is fed back through a bandpass filter to control the oscillator of the Costas loop.

Claims

1. A receiver system for receiving an FM signal generated by frequency modulating an FM radio-frequency carrier with a BPSK (binary-phase-shift-keyed) signal, said BPSK signal including data at a predetermined data rate modulated on a BPSK carrier, wherein the BPSK signal includes phase reversals in said BPSK carrier responsive to a transmitted binary data stream, said receiver system comprising, in combination,

means for detecting the BPSK signal from the FM signal, said means including circuitry for radio-frequency reception, FM demodulation, bandpass filtering to select the BPSK signal resulting from FM demodulation, and hardlimiting the selected BPSK signal, and

demodulator circuitry for detecting the binary data stream from the hardlimited BPSK signal, said demodulator circuitry including

local frequency generating means, phase shifting means, and detector means for generating multiplication products of the hardlimited BPSK signal and a locally generated frequency at approximately the frequency of the carrier of the hardlimited BPSK signal and approximately in phase and in phase quadrature with the carrier of the hardlimited BPSK signal to generate respective in-phase and quadrature-phase signals,

means for filtering and hardlimiting said in-phase signal, said hardlimited in-phase signal providing a detected binary data stream, and

feedback means for controlling said local frequency generating means, said feedback means including a feedback modulator for generating a phase error signal fed back to said local frequency generating means, and said feedback means receiving said quadrature-phase signal and modulating its polarity in response to said detected binary data stream.

2. The receiver system as claimed in claim 1, wherein said phase shifting means includes means for generating a first modulating signal at said locally generated frequency and a second modulating signal in phase quadrature with said first modulating signal, and wherein said detector means comprise:

a first exclusive-OR gate receiving said hardlimited BPSK signal and said first modulating signal and generating said in-phase signal, and

a second exclusive-OR gate receiving said hardlimited BPSK signal and said second modulating signal and generating said quadrature-phase signal.

3. The receiver system as claimed in claim 2, wherein said feedback modulator generating said phase error signal comprises an exclusive-OR gate receiving said quadrature-phase signal and said detected data and reproducing the error signal with a polarity controlled by said detected data.

4. The receiver system as claimed in claim 3, further comprising means for filtering and hardlimiting said quadrature-phase signal, said filtered and hardlimited quadrature-phase signal being received by said feedback modulator.

5. The receiver system as claimed in claim 2, wherein said phase-shifting means includes a two-stage binary ring counter.

6. The receiver system as claimed in claim 1, further comprising means responsive to the filtered in-phase signal for disabling the feeding of said phase error signal back to said local frequency generating means under low signal-to-noise conditions.

7. The receiver system as claimed in claim 6, wherein said means for disabling the feeding of said error signal back to said local frequency generating means comprises an analog transmission gate controlling transmission of said phase error signal from said feedback means to said local frequency generating means.

8. The receiver system as claimed in claim 6, wherein said means for disabling the feeding of said phase error signal back to said local frequency generating means includes means for comparing said filtered in-phase signal to high and low threshold levels to detect the low signal-to-noise conditions.

9. The receiver system as claimed in claim 8, wherein the feeding of said phase error signal back to said local frequency generating means is disabled when the amplitude of said filtered in-phase signal falls between said high and low threshold levels.

10. The receiver system as claimed in claim 1, wherein said circuitry for bandpass filtering to select the BPSK signal resulting from FM demodulation includes means for generating a selected frequency, means for multiplying signals from FM demodulation by the selected frequency to obtain product signals, and a bandpass filter for selecting the BPSK signal from the product signals.

11. The receiver system as claimed in claim 10, wherein said means for multiplying includes a balanced mixer.

12. The receiver system as claimed in claim 10, further comprising a bandpass filter through which said phase error signal is fed back to said local frequency generating means, and a low-pass filter through which said phase error signal is fed back to said means for generating a selected frequency.

13. The receiver system as claimed in claim 10, further comprising an amplitude modulation detector responsive to the signal selected by said bandpass filter, and wherein said means for generating a selected frequency includes means for receiving a tuning control signal to permit tuning of said receiver to maximize the amount of amplitude modulation detected by said amplitude modulation detector.

14. A circuit for demodulating a BPSK (binary-phase shift-keyed) signal, said BPSK signal including data at a predetermined rate modulated on a BPSK carrier, wherein the BPSK signal includes phase reversals in said BPSK carrier responsive to a transmitted binary data stream, said BPSK modulator comprising, in combination:

means for hardlimiting said BPSK signal,

local frequency generating means, phase shifting means, and detector means for generating multiplication products of the hardlimited BPSK signal and a locally generated frequency at approximately the frequency of the carrier of the hardlimited BPSK signal and approximately in phase and in phase quadrature with the carrier of the hardlimited BPSK signal to generate respective in-phase and quadrature-phase signals, wherein said detector means comprise a pair of respective exclusive-OR gates for generating said in-phase and quadrature-phase signals,

means for filtering and hardlimiting said in-phase signal, said hardlimited in-phase signal providing a detected binary data stream, and

an exclusive-OR gate for receiving said quadrature-phase signal and modulating its polarity in response to said detected binary data stream, to thereby generate a phase error signal indicating the phase difference between the phase of said locally generated frequency and the phase of the carrier of said hardlimited BPSK signal.

15. The circuit as claimed in claim 14, further comprising means for filtering and hardlimiting said quadrature-phase signal, the filtered and hardlimited quadrature-phase signal being received by said exclusive-OR gate for generating said phase error signal.

16. The circuit as claimed in claim 14, wherein said phase-shifting means includes a two-stage binary ring counter having a first output feeding a first modulating signal to one of said exclusive-OR gates of said detector means, and a second output feeding a second modulating signal to the other of said exclusive-OR gates of said detector means, said first and second modulating signals being in phase quadrature with respect to each other.

17. The circuit as claimed in claim 14, further comprising means for sensing the amplitude of said filtered in-phase signal for providing a signal indicating low signal-to-noise conditions.

18. The circuit as claimed in claim 17, further comprising means for reducing the phase difference between the phase of the carrier of the hardlimited BPSK signal and the phase of said local frequency in response to said phase error signal in the absence of said signal indicating low signal-to-noise conditions.

19. The circuit as claimed in claim 17, wherein said means for sensing the amplitude of said filtered in-phase signal comprises means for comparing said filtered in-phase signal to high and low threshold levels.

20. The circuit as claimed in claim 14, further comprising means for reducing the phase difference between the phase of the carrier of the hardlimited BPSK signal and the phase of said local frequency in response to said phase error signal.

21. The circuit as claimed in claim 20, wherein said means for reducing the phase difference includes means for adjusting the frequency of said local frequency generating means in response to said phase error signal.

22. The circuit as claimed in claim 20, wherein said means for reducing the phase difference includes means for shifting the frequency of said hardlimited BPSK signal in response to said phase error signal.

23. The circuit as claimed in claim 22, wherein said means for shifting the frequency of said hardlimited BPSK signal includes a heterodyne variable-frequency oscillator having a frequency of oscillation responsive to said phase error signal, a balanced mixer for mixing said frequency of oscillation with said BPSK signal, and a bandpass filter for selecting the frequency-shifted BPSK signal produced by said mixer, and wherein the frequency-shifted BPSK signal is hardlimited by said means for hardlimiting said BPSK signal.

24. The circuit as claimed in claim 23, further comprising an amplitude modulation detector for sensing the amplitude of the signal selected by said bandpass filter, and wherein said heterodyne variable-frequency oscillator includes a tuning control input for adjusting said frequency of oscillation for a maximum amplitude detection by said amplitude modulation detector.

25. The circuit as claimed in claim 23, further comprising a low-pass filter for filtering said phase error signal, the low-pass filtered phase error signal being fed to said heterodyne variable-frequency oscillator.

26. The circuit as claimed in claim 25, further comprising a bandpass filter for filtering said phase error signal, and further comprising means for adjusting the frequency of said local frequency generating means in response to the bandpass-filtered phase error signal, so that said local frequency generating means is phase modulated by said phase error signal to improve tracking of the BPSK signal while the average frequency of said local frequency generating means remains constant and the carrier frequency of said frequency-shifted BPSK signal remains centered within the passband of said bandpass filter for selecting the frequency-shifted BPSK signal.

27. A digital data receiver for receiving an FM broadcast band signal generated by frequency modulating an FM radio-frequency carrier with at least one SCA (Subsidiary Communications Authorization) signal, said SCA signal being generated by modulating a subcarrier with digital data, said receiver comprising, in combination,

means for radio-frequency reception of said FM broadcast band signal, means for FM demodulation, means for selecting said SCA signal resulting from FM demodulation, and means for detecting said digital data included in the selected SCA signal,

wherein said means for detecting said digital data receives said SCA signal over a substantially fixed band of frequencies, and wherein said means for selecting said SCA signal is tuneable over a relatively wide range compared to the width of said substantially fixed band of frequencies, and

wherein said means for selecting said SCA signal includes a heterodyne variable-frequency oscillator tuneable over a relatively wide range of frequencies for selecting the frequency of the SCA signal to be detected, and a balanced mixer for modulating the SCA signal resulting from FM demodulation by the frequency of oscillation of said heterodyne variable frequency oscillator, wherein the modulated SCA signal is detected by said means for detecting said digital data included in said modulated SCA signal.

28. The digital data receiver as claimed in claim 27, wherein said heterodyne variable frequency oscillator is tuneable over a frequency range of about 50 kilohertz.

29. The digital data receiver as claimed in claim 27, further comprising a high-pass filter for removing audio program material from signals resulting from FM demodulation, said high-pass filter having an output passing said SCA signal to said balanced mixer.

30. The digital data receiver as claimed in claim 27, wherein said means for FM reception is adjustably tuneable to said FM broadcast band signal, and further comprising a bandpass filter tuned to a frequency in excess of the frequency of the SCA signal resulting from FM demodulation, and an amplitude modulation detector, said bandpass filter passing noise and distortion resulting from FM demodulation to said amplitude modulation detector, said amplitude modulation detector having an output indicating the amplitude of the noise and distortion to permit tuning of said means for FM reception to minimize the indicated amplitude of the noise and distortion.

31. The digital data receiver as claimed in claim 27, further comprising a bandpass filter tuned over approximately said substantially fixed band of frequencies, said bandpass filter having an output coupled to an amplitude modulation detector for providing an SCA signal strength indication, and wherein said heterodyne variable frequency oscillator includes a frequency control input for tuning said heterodyne variable frequency oscillator to maximize the SCA signal strength indication.

32. The digital data receiver as claimed in claim 31, further comprising a hardlimiter receiving the output of said bandpass filter and hardlimiting the subcarrier information signal, the hardlimited subcarrier information signal being received by said means for detecting said digital data included in said SCA signal.

33. The digital data receiver as claimed in claim 27, wherein said SCA signal is generated by modulating the phase of said SCA subcarrier, and said means for detecting said digital data includes means for coherently detecting said digital data by comparing said modulated SCA signal to a local reference carrier and means for generating a phase error signal, and a low-pass filter through which said phase error signal is fed back to adjust the frequency of said heterodyne variable frequency oscillator.

34. The digital data receiver as claimed in claim 33, wherein said low-pass filter is an integrating low-pass filter.

35. The digital data receiver as claimed in claim 33, wherein said means for detecting said digital data further includes a local oscillator for generating said local reference carrier, said local oscillator having a frequency control input, and a bandpass filter through which said phase error signal is fed back to said frequency control input.

36. The digital data receiver as claimed in claim 33, wherein said means for detecting said digital data includes means for sensing the amplitude of the portion of the modulated SCA signal that is phase coherent with said reference carrier, and means for inhibiting the feeding back of said phase error signal in response to the sensed amplitude falling below a threshold level.

37. The digital data receiver as claimed in claim 36, wherein said means for detecting said digital data includes an exclusive-OR gate for comparing said modulated SCA signal to said local reference carrier to provide an in-phase signal, and a low-pass filter for filtering said in-phase signal to provide a signal indicating the portion of the modulated SCA signal that is phase coherent with said local reference carrier.

38. A digital data receiver for receiving an FM broadcast band signal generated by frequency modulating an FM radio-frequency carrier with at least one SCA (Subsidiary Communications Authorization) signal, said SCA signal being generated by phase modulating a subcarrier with digital data, said receiver comprising, in combination,

means for radio-frequency reception of said FM broadcast band signal, means for FM demodulation, and means for detecting said digital data included in the SCA signal resulting from FM demodulation,

wherein said means for detecting said digital data includes means for coherently detecting said digital data by comparing the phase of said SCA signal resulting from FM demodulation to the phase of a local reference carrier, means for generating a phase error signal, and means for adjusting the phase of the local reference carrier relative to the phase of the subcarrier of the SCA signal resulting from FM demodulation, wherein said phase error signal is filtered and fed back to said means for adjusting the phase in order to maintain a phase-lock condition, and

wherein said means for detecting said digital data includes means for sensing the amplitude of the portion of the SCA signal resulting from FM demodulation that is phase coherent with said reference carrier, and means for inhibiting the feeding back of said phase error signal in response to the sensed amplitude falling below a threshold level, to thereby maintain the phase of the local reference carrier substantially fixed during low signal-to-noise conditions.

39. The digital data receiver as claimed in claim 38, wherein said means for detecting said digital data includes an exclusive-OR gate for comparing said signal resulting from FM demodulation to a reference signal to provide an in-phase signal, and a low-pass filter for filtering said in-phase signal to provide a signal indicating the portion of the SCA signal resulting from FM demodulation that is phase coherent with said local reference carrier.

40. The digital data receiver as claimed in claim 39, wherein said means for detecting said digital data further includes means for generating a selected frequency, means for multiplying signals from FM demodulation by the selected frequency to obtain product signals, a bandpass filter for selecting the SCA signal from the product signals, and a limiter for hardlimiting the selected SCA signal, the hardlimited SCA signal being fed to said exclusive-OR gate, wherein said means for adjusting the phase of the local reference carrier includes means responsive to the filtered phase error signal for adjusting the frequency generated by said means for generating a selected frequency.

41. The digital data receiver as claimed in claim 40, wherein said means for adjusting the phase of the local reference carrier further includes means for adjusting the frequency of said reference signal in response to the filtered phase error signal.

42. The digital data receiver as claimed in claim 41, wherein the frequency generated by the said means for generating a selected frequency is adjusted in response to low-pass filtering of said phase error signal, and the frequency of said reference signal is adjusted in response to bandpass filtering of said phase error signal.

43. A method of tuning an FM receiver of the kind having circuits for radio-frequency reception including a tuning means for tuning the circuits for reception of an FM signal at a preassigned carrier frequency, said circuits for radio-frequency reception also including a demodulator for demodulating said FM signal, wherein said FM signal is generated by frequency modulating a carrier at said preassigned carrier frequency with a bandlimited signal including frequencies up to a certain maximum frequency, and wherein said demodulator provides a demodulated signal including said bandlimited signal and noise and distortion at frequencies in excess of said maximum frequency, said method tuning said receiver so as to receive said FM signal with a minimum of distortion in said demodulated signal and comprising the steps of

(a) selecting the noise and distortion at certain frequencies in excess of said maximum frequency by bandpass filtering said demodulated signal to selected said certain frequencies in excess of said maximum frequency, and by detecting the amplitude of the signal including the selected frequencies, and

(b) operating said tuning means so that the noise and distortion measured in step (a) is a minimum.

44. The method as claimed in claim 43, wherein said tuning means includes electronic tuning means responsive to a tuning control voltage and said tuning control voltage is adjusted by a microcomputer which reads the detected amplitude.

45. The method as claimed in claim 44, wherein said microcomputer successively reads the detected amplitude and changes the tuning control voltage to a different value, again reads the detected amplitude, compares the newly detected amplitude to the amplitude having been stored, and resets the tuning control voltage to the previous value in the event that the amplitude having been stored is less than the newly detected amplitude.