Frequency synthesizer with spur compensation

• US 4,816,774 A
• Filed: 06/03/1988
• Issued: 03/28/1989
• Est. Priority Date: 06/03/1988
• Status: Expired due to Term

• Current Assignee: Quarterhill Inc. (f/k/a Wi-LAN Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Martin, Frederick L.
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US07/202,065
• Time in Patent Office: 298 Days
• Field of Search: 331/1 A, 331/16, 331/18, 331/25, 455/260
• US Class Current: 331/1.00A
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

A synthesizer circuit with spur compensation utilizes fractional division in the synthesizer loop. Two accumulators are utilized for determining the divisor value N. The capacity of the two accumulators is selectable. An offset value is selectively introduced into the accumulators in order to produce a waveform having an acceptable spurious content.

Claims

1. A frequency synthesizer for providing a synthesized output frequency f_O comprising:

a synthesizer loop including a programmable divider;

a divider control means providing divider values to the programmable divider, the divider control means providing varying values to the programmable divider for fractional division to produce a desired output frequency f_O, and including first and second accumulator means;

the first accumulator means including an input for receiving data, a first output for varying the divide value, and a second output for providing data to the second accumulator means, and

the second accumulator means including an input connected to the second output of the first accumulator means and an output for varying the divide value;

the first and second accumulator means each having a variable capacity.

2. A frequency synthesizer as defined in claim 1, further including:

means for providing an offset value to the first and second accumulator means.

3. A frequency synthesizer as defined in claim 2, in which:

said means for providing an offset value includes a me1mory means, the memory means having offset information for each desired output frequency f_O.

4. A frequency synthesizer as defined in claim 3, in which:

said memory means includes capacity information for determining the capacity of said first and second accumulator means.

5. A frequency synthesizer as defined in claim 1, in which:

each of the accumulator means includes a first adder having first and second inputs, a sum output, and a carry output,

a second adder having first and second inputs, a sum output, and a carry output, the output of the first adder being operatively connected to the first input of the second adder,

a multiplexer having first and second inputs operatively connected to the outputs of the first and second adders respectively and having an output, and

a latch having an input operatively connected to the output of the multiplexer and an output operatively connected to the second input of the first adder,

the first input of the first adder comprises an input of the accumulator means, the second input of the second adder comprises a capacity input of the accumulator means, the output of the multiplexer comprises an output of the accumulator means, and the carry outputs of the first and second adders cooperatively comprise a carry output of the accumulator means.

6. A frequency synthesizer for providing a synthesized output frequency f_O comprising:

a synthesizer loop including a programmable divider;

a divider control means providing divider values to the programmable divider, the divider control means providing varying values to the programmable divider for fractional division to produce a desired output frequency f_O, and including first and second accumulator means;

the first accumulator means including an input for receiving data, a first output for varying the divide value, and a second output for providing data to the second accumulator means, and

the second accumulator means including an input connected to the second output of the first accumulator means and an output for varying the divide value;

means for providing an offset value to the first and second accumulator means.