Method of recording in a disk memory and disk memory system

• US 4,817,035 A
• Filed: 03/15/1985
• Issued: 03/28/1989
• Est. Priority Date: 03/16/1984
• Status: Expired due to Term

• Current Assignee: CII Honeywell Bull
• Original Assignee: CII Honeywell Bull
• Inventors: Timsit, Claude
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Kriess, Kevin A.
• Application Number:
  US06/712,174
• Time in Patent Office: 1,474 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 371/8, 371/10, 360/25, 360/26, 360/22, 360/98
• US Class Current: 714/54
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11B 20/1833 by adding special lists or symbols to the coded information G11B20/1806, G11B20/1866 take precedence

Abstract

A method of recording numerical information in a plurality of disk units, in which the bits of each word of numerical information are transmitted simultaneously, each bit being allocated to a unit associated with the weight of that bit in that word, and a memory system for implementing the method, including a main controller (2) provided with a selector enabling the distribution and synchronization of the information signals.

Claims

1. A method of writing and reading numerical information in a mass memory comprising a plurality of disk units (3), each disk unit being capable of containing one or a plurality of disks (7), said mass memory being controlled by at least one disk controller, each word of numerical information comprising a plurality of bits and being associated with a logical address, characterized in that at the time of the transfer of information to or from disk units (3), the bits making up one word of information are transmitted simultaneously, each bit being allocated to a disk unit associated with the position of said bit in said word, in order to be written or read synchronously with the other bits of the same word at a physical address which is a univocal function of the logical address of said word of information, said physical address defining, for each disk unit, the effective location where said bit will be written or read, that is, defining the disk of said unit, in the case where the unit includes more than one disk, a number of a track of said more than one disk and the location of said bit on said track, said method being further characterized in that for writing a block of information, that is, a sequence of words of information associated with a block address and arriving at each disk unit in the form of a sequence of bits associated with the same block address, each bit of said sequence is first temporarily recorded in a memory associated with said each disk unit, and then physically recorded on a disk of said unit and in that for reading a block of information from said disk, a reverse operation is performed, said method being further characterized in that before transferring to said disk the sequence of numerical information transmitted from said memory associated with said disk unit, longitudinal error detection or correction bits (Kli-Kyi) are calculated and added to said sequence, and in that before writing into the memory the sequence of numerical information coming from said disk, an operation of detecting longitudinal error and correcting them if necessary is effected.

2. A method according to claim 1, characterized in that for each word of information to be written, transversal error detection or correction bits are calculated, associated with the bits of said word of information, each transversal error detection or correction bit being transmitted synchronously with the bits of said word to a disk unit associated with the position of said bit of said information in order to be written there, and in that for each information to be read, an operation of detection or correction of transversal errors is effected with the aid of said transversal error detection or correction bits before the bits of said information are transmitted synchronously via the data bus.

3. A method according to claim 2, characterized in that upon the detection, in accordance with predetermined criteria, of permanent defects affecting recording in one or a plurality of disk units, this status triggers a process of reconfiguration, if the correction of the defects is possible with the aid of transversal error correction bits, according to which process the entirety of what is recorded in the defective disk unit or units is retranscribed, after said correction of transversal errors, onto one or a plurality of reserve disk units.

6. A method according to claim 3, characterized in that the result of said operations of detecting transversal and/or longitudinal errors serves to establish said criterion for permanent defects affecting recording into at least one disk unit if, after one or more rereadings of the tracks, transversal and/or longitudinal errors are still detected.

7. A method according to claim 2, characterized in that for writing a block of information, that is, a sequence of words of information associated with a block address and arriving at each disk unit in the form of a sequence of bits associated with the same block address, each bit of said sequence intended for being recorded in the corresponding disk unit is first inscribed, at an address in memory which is a univocal function of the block address and of the place of the bit in said sequence of bits, into a direct access memory associated with said disk units, and when said sequence of bits has been entirely inscribed into said memory, the binary information then contained in said memory is read in sequence and transmitted in series in order to be recorded on a track of one of the disks of said unit, said disk and said track of said disk being determined as a function of said block address, the memory address of the first bit transmitted being determined as a function of the number of the first sector of said track encountered by the recording head, the sequential reading of said memory being effected in accordance with a cyclical sequence,

and in that for reading a word of information associated with a given logical address, the bits comprising this information beginning at the set of memories associated with said disk units at memory addresses which are a function of the logical address, are synchronously read immediately, if the information is present in the set of memories or, in the contrary case, after retranscription into each memory of the entirety of the binary information contained on the track associated with said logical address, said retranscription being effected beginning at the first sector of said track encountered by the reading head.

8. A method according to claim 7, characterized in that before recording onto a disk track the sequence of binary information transmitted beginning at the memory associated with a disk unit, longitudinal error detection or correction bits (K_1i -K_yi) are calculated and added to said sequence,

and in that before writing into the memory the binary information coming from one track, an operation of detecting longitudinal errors and correcting them if necessary is effected.

10. A method according to claim 8, characterized in that the result of said operations of detecting transversal and/or longitudinal errors serves to establish said criterion for permanent defects affecting recording into at least one disk unit if, after one or more rereadings of the tracks, transversal and/or longitudinal errors are still detected.

4. A method of writing and reading numerical information in a mass memory comprising a plurality of disk units (3), each disk unit being capable of containing one or a plurality of disks (7), said mass memory being controlled by at least one disk controller, each word of numerical information comprising a plurality of bits and being associated with a logical address, characterized in that at the time of the transfer of information to or from the disk unit (3), the bits making up one word of information are transmitted simultaneously, each bit being allocated to a disk unit associated with the position of said bit in said word, in order to be written or read synchronously with the other bits of the same word at a physical address which is a univocal function of the logical address of said word of information, said physical address defining, for each disk unit, the effective location where said bit will be written or read, that is, defining the disk of said unit, in the case where the unit includes more than one disk, a number of a track of said more than one disk and the location of said bit on said track,

said method being further characterized in that for writing a block of information, that is, a sequence of words of information associated with a block address and arriving at each disk unit in the form of a sequence of bits associated with the same block address, each bit of said sequence intended for being recorded in the corresponding disk unit is first inscribed, at an address in memory which is a univocal function of the block address and of the place of the bit in said sequence of bits, into a direct access memory associated with said disk units, and when said sequence of bits has been entirely inscribed into said memory, the numerical information then contained in said memory is read in sequence and transmitted in series in order to be recorded on a track of one of the disks of said unit, said disk and said track of said disk being determined as a function of said block address, the memory address of the first bit transmitted being determined as a function of the number of the first sector of said track encountered by the recording head, the sequential reading of said memory being effected in accordance with a cyclical sequence,

and in that for reading a word of information associated with a given logical address, the bits comprising this information beginning at the set of memories associated with said disk units at memory addresses which are a function of the logical address, are synchronously read immediately, if the information is present in the set of memories or, in the contrary case, after retranscription into each memory of the entirety of the numerical information contained on the track associated with said logical address, said retranscription being effected beginning at the first sector of said track encountered by the reading head.

11. A method according to claim 4, characterized in that before recording onto a disk track the sequence of binary information transmitted beginning at the memory associated with a disk unit, longitudinal error detection or correction bits (K_1i -K_yi) are calculated and added to said sequence,

and in that before writing into the memory the binary information coming from one track, an operation of detecting longitudinal errors and correcting them if necessary is effected.

12. A method according to claim 11, characterized in that the result of said operations of detecting transversal and/or longitudinal errors serves to establish said criterion for permanent defects affecting recording into at least one disk unit if, after one or more rereadings of the tracks, transversal and/or longitudinal errors are still detected.

5. A method of writing and reading numerical information in a mass memory comprising a plurality of disk units (3), each disk unit being capable of containing one or a plurality of disks (7), said mass memory being controlled by at least one disk controller, each word of numerical information comprising a plurality of bits and being associated with a logical address, characterized in that at the time of the transfer of information to or from the disk units (3), the bits making up one word of information are transmitted simultaneously, each bit being allocated to a disk unit associated with the position of said bit in said word, in order to be written or read synchronously with the other bits of the same word at a physical address which is a univocal function of the logical address of said word of information, said physical address defining, for each disk unit, the effective location where said bit will be written or read, that is, defining the disk of said unit, in the case where the unit includes more than one disk, the number of a track of said more than one disk and the location of said bit on said track, and

further characterized in that each bit of said word of information is first temporarily recorded in a memory associated with said disk and then is physically recorded on a disk of said unit, and

in that for reading a word of information from said disk, a reverse operation is preformed,

and further characterized in that before recording onto a disk track the block of numerical information transmitted beginning at the memory associated with a disk unit, longitudinal error detection or correction bits (K_1i -K_yi) are calculated and added to said block of numerical information,

and in that before writing into the memory the numerical information coming from one track, an operation of detecting longitudinal errors and correcting them if necessary is effected.

9. A method according to claim 5, characterized in that the result of said operations of detecting transversal and/or longitudinal errors serves to establish said criterion for permanent defects affecting recording into at least one disk unit if, after one or more rereadings of the tracks, transversal and/or longitudinal errors are still detected.

13. A memory system, including a plurality of disk units (3) connected to the exterior via first lines (D1, A1, C1) for transmitting data, address and control signals, characterized in that said disk units (3) are controlled by a main controller (2) cooperating via second lines (D2, A2, C2) for transmitting data, address and control signals with a plurality of disk controllers (4), each of which controls one disk unit (3) containing one or a plurality of disks (7), and in that said main controller (2) includes means (21, 23, 25, 29, 30) for synchronizing a simultaneous transfer of bits forming each word of information to be written or read in said disk units (3) and means for commanding said disk controllers (4) to write or read simultaneously, each disk controller (4) thus validated being able to process, for each word of information, a single bit of said word of information and to transmit or receive said bit via a line (8) connected to the main controller,

said memory system being further characterized in that said main controller including means (21, 25, 26, 31) for determining, based on a logical address associated with a word of information to be read or written, a logical disk address being a logical disk number, a logical track number and a complementary address, said logical disk address being transmitted to each disk controller via said lines, and means for giving the order to read or write to said controllers via said lines,

and in that each disk controller (4) includes means for writing the information received over its line into the associated disk unit (3), at a physical address which is a univocal function of the logical disk address and means for reading in this disk unit the information recorded at said physical address and for transmitting said information over the line.

14. A memory system according to claim 13, characterized in that each memory (9, 302) associated with a disk unit (3) is addressable either by the main controller (2) or by the disk controller (4) of said unit, the addressing via the main controller (2) being determined by said complementary address.

15. A memory system according to claim 13, characterized in that the main controller includes means (22) for calculating for each word of information, based on the bits of said word of information received from exterior over the said first lines, bits for detecting or correcting transversal errors (C_jl -C_jk), intended to be recorded separately into disk units (3) allocated to these error detection or correction bits.

16. A memory system according to claim 13, characterized in that each disk unit (3) includes a read-write direct access memory (9, 302) intended for temporarily recording a sequence of bits coming from the second lines before being transmitted to a disk, or serving to temporarily record a sequence of bits coming from a disk before being transmitted to said lines.

17. A memory system according to claim 13, characterized in that it includes reserve disk units (3-(P+1)-3-N) and a unit (23) for selecting the lines of said main controller (2), enabling a reconfiguration of the system in the event of a breakdown of one or more disk units (3).

18. A memory system according to claim 17, characterized in that said selection unit (23) comprises a plurality of multiplexers (23-1-23-P), each being associated with one normal disk unit (3-1-3-P) and connected, first, to said disk unit (3-1-3-P) and, second, to the reserve disk units (3-(P+1)-3-N), under the control of the main controller (2).

19. A memory system according to claim 13, characterized in that each disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.

20. A memory system according to claim 15, characterized in that each disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.

21. A memory system according to claim 16, characterized in that each disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.

22. A memory system according to claim 15, characterized in that each disk unit (3) includes a read-write direct access memory (9, 302) intended for temporarily recording a sequence of bits coming from the second lines before being transmitted to a disk, or serving to temporarily record a sequence of bits coming from a disk before being transmitted to said lines.

23. A memory system according to claim 22, characterized in that each memory (9, 302) associated with a disk unit (3) is addressable either by the main controller (2) or by the disk controller (4) of said unit, the addressing via the main controller (2) being determined by said complementary address.

24. A memory system according to claim 15, characterized in that it includes reserve disk units (3-(P+1)-3-N) and a unit (23) for selecting the lines of said main controller (2), enabling a reconfiguration of the system in the event of a breakdown of one or more disk units (3).

25. A memory system according to claim 24, characterized in that said selection unit (23) comprises a plurality of multiplexers (23-1-23-P), each being associated with one normal disk unit (3-1-3-P) and connected, first, to said disk unit (3-1-3-P) and, second, to the reserve disk units (3-(P+1)-3-N), under the control of the main controller (2).

26. A memory system according to claim 16, characterized in that it includes reserve disk units (3-(P+1)-3-N) and a unit (23) for selecting the lines of said main controller (2), enabling a reconfiguration of the system in the event of a breakdown of one or more disk units (3).

27. A memory system according to claim 26, characterized in that said selection unit (23) comprises a plurality of multiplexers (23-1-23-P), each being associated with one normal disk unit (3-1-3-P) and connected, first, to said disk unit (3-1-3-P) and, second, to the reserve disk units (3-(P+1)-3-N), under the control of the main controller (2).

28. A memory system according to claim 22, characterized in that it includes reserve disk units (3-(P+1)-3-N) and a unit (23) for selecting the lines of said main controller (2), enabling a reconfiguration of the system in the event of a breakdown of one or more disk units (3).

29. A memory system according to claim 28, characterized in that said selection unit (23) comprises a plurality of multiplexers (23-1-23-P), each being associated with one normal disk unit (3-1-3-P) and connected, first, to said disk unit (3-1-3-P) and, second, to the reserve disk units (3-(P+1)-3-N), under the control of the main controller (2).

30. A memory system according to claim 14, characterized in that it includes reserve disk units (3-(P+1)-3-N) and a unit (23) for selecting the lines of said main controller (2), enabling a reconfiguration of the system in the event of a breakdown of one or more disk units (3).

31. A memory system according to claim 30, characterized in that said selection unit (23) comprises a plurality of multiplexers (23-1-23-P), each being associated with one normal disk unit (3-1-3-P) and connected, first, to said disk unit (3-1-3-P) and, second, to the reserve disk units (3-(P+1)-3-N), under the control of the main controller (2).

32. A memory system according to claim 23, characterized in that it includes reserve disk units (3-(P+1)-3-N) and a unit (23) for selecting the lines of said main controller (2), enabling a reconfiguration of the system in the event of a breakdown of one or more disk units (3).

33. A memory system according to claim 32, characterized in that said selection unit (23) comprises a plurality of multiplexers (23-1-23-P), each being associated with one normal disk unit (3-1-3-P) and connected, first, to said disk unit (3-1-3-P) and, second, to the reserve disk units (3-(P+1)-3-N), under the control of the main controller (2).

34. A memory system according to claim 22, characterized in that said disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.

35. A memory system according to claim 14, characterized in that each disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.

36. A memory system according to claim 23, characterized in that each disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.

37. A memory system according to claim 17, characterized in that each disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.

38. A memory system according to claim 24, characterized in that each disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.

39. A memory system according to claim 26, characterized in that each disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.

40. A memory system according to claim 28, characterized in that each disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.

41. A memory system according to claim 30, characterized in that each disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.

42. A memory system according to claim 32, characterized in that each disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.

43. A memory system according to claim 18, characterized in that each disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.

44. A memory system according to claim 25, characterized in that each disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.

45. A memory system according to claim 27, characterized in that each disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.

46. A memory system according to claim 29, characterized in that each disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.

47. A memory system according to claim 31, characterized in that each disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.

48. A memory system according to claim 33, characterized in that each disk controller (4) includes a processing unit (304) operating with data in parallel and a series/parallel converter serving as an interface for the main controller (2) and controlled by said main controller.