High speed RAM based data serializers

• US 4,817,054 A
• Filed: 12/04/1985
• Issued: 03/28/1989
• Est. Priority Date: 12/04/1985
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Keswick, Paul D., Banerjee, Pradip
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): GOSSAGE, GLENN
• Application Number:
  US06/805,164
• Time in Patent Office: 1,210 Days
• Field of Search: 365/221, 365/219, 365/239, 365/240, 365/189, 365/78, 365/230, 365/233, 340/750, 340/799, 340/801
• US Class Current: 365/189.02
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters

Abstract

Multiple bit parallel data serializers are described for accessing data serially through a port at high video data rates. The serializer preferably comprises a buffer array for storing data at a plurality of SRAM memory locations, sense amplifiers for sensing the stored data, an address decoder for selecting a predetermined memory location of the buffer array for data access by the sense amplifiers, a data latch for the latched buffering of data prior to output to the serial port and a control gate for enabling the gated transfer of data between the sense amplifiers and the output latch.

Claims

1. Apparatus for storing data and for providing data serially at high data rates, said apparatus comprising:

(a) means for storing data at a plurality of memory locations;

(b) means, responsive to a first enabling signal, for sensing data stored by said storing means, said sensing means provided sensed data;

(c) means, responsive to a second enabling signal, for selectively coupling a memory location of said storing means to said sensing means to permit the sensing of the data stored thereby;

(d) means, responsive to a third enabling signal, for latching said sensed data, said latching means being coupled to said sensing means;

(e) means, responsive to a fourth enabling signal, for generating an address signal identifying a memory location of said storing means, said generating means providing said address signal to said selectively coupling means; and

(f) control means for providing said first, second, third and fourth enabling signals, said control means providing said first, second, third and fourth enabling signals such that;

(i) said generating means generates a first predetermined address signal while said selectively coupling means couples said sensing means to sense the data at a memory location corresponding to a second predetermined address signal, said second predetermined address signal having been generated prior to said first predetermined address signal, and said latching means receives the sensed data corresponding to said second predetermined address signal; and

(ii) said latching means latches said sensed data corresponding to said second predetermined address signal at least until said selectively coupling means receives said first predetermined address signal and couples said sensing means to the memory location corresponding to said first predetermined address signal.

2. The apparatus of claim 1 wherein said latching means includes a first latch coupled to said sensing means for receiving sensed data and a second latch coupled to said first latch for receiving sensed data, wherein said first latch is responsive to said third enabling signal, wherein said second latch is responsive to a fifth enabling signal, and wherein said control means provides said fifth enabling signal such that said second latch latches the sensed data corresponding to a third predetermined address signal prior to the second data corresponding to said second predetermined address signal being received by said first latch, said third predetermined address signal having been generated prior to said second predetermined address signal.

3. Apparatus for storing data and for providing data serially at high video data rates, said apparatus comprising:

(a) first and second serializer units each including;

(i) means for storing data at a plurality of memory locations;

(ii) means, responsive to a first enabling signal, for sensing data stored by said storing means, said sensing means providing sensed data;

(iii) means, responsive to a second enabling signal, for selectively coupling a memory location of said storing means to said sensing means to permit the sensing of the data stored thereby;

(iv) means, responsive to a third enabling signal, for latching said sensed data, said latching means being coupled to said sensing means;

(b) means, responsive to an address control signal, for generating an address signal identifying a memory location of storing means of said first and second serializer units, said generating means providing said address signal to said selectively coupling means of said first and second serializer units;

(c) means, responsive to a multiplexor control signal, for multiplexing sensed data, said multiplexing means being coupled to the latching means of said first and second serializing units for the receipt of sensed data; and

(d) control means for providing said first and second serializing units with respective ones of said first, second, and third enabling signals, said control means further providing said address control and said multiplexor control signals, said control means providing said first and second serializing units with respect ones of said first, second, third and fourth enabling signals such that for the respective first and second serializing units;

(i) said generating means generates a first predetermined address signal while said selectively coupling means couples said sensing means to sense the data at a memory location corresponding to a second predetermined address signal, said second predetermined address signal having been generated prior to said first predetermined address signal, and said latching means receives the sensed data corresponding to said second predetermined address signal; and

(ii) said latching means latches said sensed data corresponding to said second predetermined address signal at least until said selectively coupling means receives said first predetermined address signal and couples said sensing means to the memory location corresponding to said first predetermined address signal.

4. The apparatus of claim 3 wherein said latching means includes a first latch coupled to said sensing means for receiving sensed data and a second latch coupled to said first latch for receiving sensed data, wherein said first latch is responsive to said third enabling signal, wherein said second latch is responsive to a fifth enabling signal, and wherein said control means provides said fifth enabling signal such that said second latch latches the sensed data corresponding to a third predetermined address signal prior to the sensed data corresponding to said second predetermined address signal being received by said first latch, said third predetermined address signal having been generated prior to said second predetermined address signal.

5. A high speed data serializer for providing multiple bit parallel serialized data during a memory cycle, said serializer comprising:

(a) a plurality of memory array planes, each said memory array plane including respective arrays of first and second memory cells, each said memory array plane providing a parallel bit of the multiple parallel bit serialized data;

(b) a plurality of first and second memory cell access selectors for providing access selection control data determinative of the memory cells of respective one of said memory array planes to be accessed during a predetermined memory cycle, each said first and second memory cells access selectors including a plurality of first latch means for storing said access selection control data;

(c) a plurality of first and second sense amplifier means, respectively coupled to said first and second memory cell access selectors, for sensing the data stored by the memory cells of respective ones of said memory array planes accessed during said predetermined memory cycle as determined in response to said access selection control data, each said first and second sense amplifier means including a plurality of second latch means for storing data sensed by said first and second sense amplifier means during said predetermined memory cycle;

(d) a plurality of data multiplexers having first and second data inputs and a multiplexed data output, said first and second multiplexer data inputs of each said data multiplexer being coupled to receive data from respective ones of said first and second sense amplifier means of a respective memory array plane, said multiplexed data outputs of said data multiplexers providing said parallel bits of the multiple bit parallel serialized data; and

(e) control means for providing a plurality of control signals with respect to a series of memory cycles including a first control signal to initiate the generation of access selection control data during a memory cycle prior to said predetermined memory cycle, a second control signal, subsequent to said first control signal, to enable the latching of access selection control data by said first latch means, a third control signal, subsequent to said second control signal, to enable said sense amplifier means and said second latch means during said predetermined memory cycle and prior to provision of said second control signal with respect to a memory cycle subsequent to said predetermined memory cycle.

6. The high speed data serializer of claim 5 wherein said control means provides said first, second and third control signals to said first memory cell access selectors and said first sense amplifier means and to said second memory cell access selectors and said second sense amplifier means such that the respective memory cycles are offset, relative to one another by a half memory cycle.

7. The high speed data serializer of claim 6 further comprising:

(a) first and second data lines respectively coupling each of said first and second memory cell access selectors with each of said first and second sense amplifier means, said first and second data lines providing a transfer path for data from the selected ones of said first and second memory cells to their respective first and second sense amplifier means; and

(b) means for clearing data from said first and second data lines during alternating half memory cycles, said clearing means being responsive to a fourth control signal, and wherein said fourth control signal is provided by said control means.

8. The high speed data serializer of claim 7 wherein each of the first and second sense amplifier means further comprises a plurality of third latch means for storing data sensed by said first and second sense amplifier means during a memory cycle prior to said predetermined memory cycle.

9. The high speed data serializer of claim 8 further comprising a plurality demultiplexers each having a data input for receiving high speed serialized data and first and second data outputs respectively coupled to said first and second data lines for providing demultiplexed serial data thereto.

10. The high speed data serializer of claim 9 wherein said plurality of first and second memory cell access selectors include a sequential count valve counter for generation of said access selection control data thereby.

11. The high speed data serializer of claim 10 wherein the initial sequential count value of each of said sequential count value counters is programmable.