Semiconductor memory circuit including bias voltage generator

• US 4,817,055 A
• Filed: 08/15/1986
• Issued: 03/28/1989
• Est. Priority Date: 08/16/1985
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Arakawa, Hideki, Kawashima, Hiromi
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): Bowler, Alyssa H.
• Application Number:
  US06/896,785
• Time in Patent Office: 956 Days
• Field of Search: 307/304, 307/297, 307/450, 307/200 B, 365/189, 365/226
• US Class Current: 365/185.23
• CPC Class Codes: G05F 3/24 wherein the transistors are of the field-effect type only G05F3/205, G05F3/26, G05F3/30 take precedence
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A semiconductor memory circuit includes therein a bias voltage generator which produces a bias voltage to be supplied to a control gate of a field effect transistor (FET) which forms a part of each memory cell in the semiconductor memory circuit. The bias voltage generator is comprised of a bias voltage generating source which is sandwiched by first and second FET'"'"'s. The second FET operates to stop a driving current flowing through the bias voltage generating source, in a standby mode, and the first FET operates to produce an output voltage near to the bias voltage. The bias voltage is generated by the bias voltage generating source when both the first and second FET'"'"'s are turned ON, in an active mode, and the driving current flows therethrough.

Claims

1. A semiconductor memory circuit having an active mode and a standby mode, said semiconductor memory circuit comprising:

a plurality of memory cells, each including a field effect transistor (FET) having a control gate, as a memory transistor;

a first power supply line for supplying a first power supply voltage;

a second power supply line for supplying a second power supply voltage; and

a bias voltage generator, connected to said memory cells, for supplying at least a predetermined bias voltage to each said control gate in the active mode, said bias voltage generator including,

a bias voltage generating source having a current inlet, a current outlet, and an output terminal for outputting the predetermined bias voltage when a driving current flows from the current inlet to the current outlet,

a first FET, connected between said first power supply line and the current inlet of the bias voltage generating source, having a gate receiving a common input signal which selectively defines one of the active and standby modes, the first FET being turned on regardless of the status of the input signal, and

a second FET, connected between said second power supply line and the current outlet of the bias voltage generating source, the second FET being turned on during the active mode and turned off during the standby mode, whereby an output voltage near to the predetermined bias voltage is supplied from the output terminal of said bias voltage generator and the driving current is cut by the second FET.

2. A semiconductor memory circuit as set forth in claim 1, wherein said first FET is an n-channel depletion type FET and said second FET is an n-channel enhancement type FET.

3. A semiconductor memory circuit as set forth in claim 2, wherein said n-channel depletion type FET has a threshold voltage which defines said output voltage to be produced in said standby mode and is near to said predetermined bias voltage.

4. A semiconductor memory circuit as set forth in claim 3, wherein said common input signal is made "H" and "L" level in response to said active mode and said standby mode, respectively, and said input signal can be substituted by a usual chip enable signal or chip selection signal.

5. A semiconductor memory circuit as set forth in claim 4, wherein said bias voltage generating source is comprised of at least one pair of series-connected FET'"'"'s, an intermediate connecting point of which is led to an output terminal for producing said output voltage or said bias voltage.

6. A semiconductor memory circuit as set forth in claim 5, wherein said pair of series-connected FET'"'"'s comprises a depletion type FET and an enhancement type FET, and the gates thereof are commonly connected to said intermediate connecting point.

7. A semiconductor memory circuit as set forth in claim 5, wherein said pair of series-connected FET'"'"'s are depletion type FET'"'"'s, and the gates thereof are commonly connected to said intermediate connecting point.

8. A semiconductor memory circuit as set forth in claim 5, wherein said pair of series-connected FET'"'"'s comprise a third FET and a fourth FET, the gate of the third FET being connected to the source of said first FET and the gate of the fourth FET being connected to said intermediate connecting point.

9. A semiconductor memory circuit as set forth in claim 8, wherein said third and fourth FET'"'"'s are both enhancement type FET'"'"'s or both depletion type FET'"'"'s.

10. A semiconductor memory circuit as set forth in claim 8, wherein said third and fourth FET'"'"'s are depletion type and enhancement type FET'"'"'s, respectively.

11. A semiconductor memory circuit as set forth in claim 5, wherein said pair of series-connected FET'"'"'s are a depletion type FET, at said current inlet of said bias voltage generating source, and an enhancement type FET, at said current outlet of said bias voltage generating source, both FET'"'"'s having commonly connected gates, the pair of series-connected FET'"'"'s are further connected in parallel with another pair of series-connected FET'"'"'s set which are both depletion type FET'"'"'s, one of said depletion type FET'"'"'s having a gate connected with the drain thereof, and the other of said depletion type FET'"'"'s having a gate connected with the drain thereof and also with said commonly connected gates.