Byte write error code method and apparatus

• US 4,817,095 A
• Filed: 05/15/1987
• Issued: 03/28/1989
• Est. Priority Date: 05/15/1987
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Chisvin, Lawrence A., Smelser, Donald W., Stegeman, James C.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): BEAUSOLIEL JR, ROBERT W
• Application Number:
  US07/050,839
• Time in Patent Office: 683 Days
• Field of Search: 371/13, 371/38, 371/51, 365/200
• US Class Current: 714/764
• CPC Class Codes: G06F 11/1056 Updating check bits on partial write, i.e. read/modify/write
• CPC Class Codes: H03M 13/00 Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes error detection or error correction for analogue/digital, digital/analogue or code conversion H03M1/00 – H03M11/00; specially adapted for digital computers G06F11/08; for information storage based on relative movement between record carrier and transducer G11B, e.g. G11B20/18; for static stores G11C
• CPC Class Codes: H03M 13/13 Linear codes

Abstract

A method and apparatus for error detection is disclosed. A data word and its check bits are read from memory, and new check bits are generated form the data word read. A logical operation is performed between the new check bits and the check bits read from memory to generate a syndrome. The syndrome is decoded to detect the presence or absence of an uncorrectable error. If an uncorrectable error is detected, a logical operation is performed between the new check bits and a byte write error code to generate a third set of check bits, which are then written into memory along with the data word.

Claims

1. A method for error detection comprising the steps of:

(a) reading a data word from a memory;

(b) reading from the memory a first set of check bits associated with the data word read;

(c) generating a second set of check bits from the data word that has been read from the memory;

(d) performing a first logical operation between the first set of check bits and the second set of check bits to generate a syndrome;

(e) decoding the syndrome in order to detect the presence or absence of an uncorrectable error, and upon the detection of an uncorrectable error, modifying the check bits to indicate such uncorrectable error.

2. The method recited in claim 1, wherein the modification comprises:

(i) performing a second logical operation between the second set of check bits and a byte write error code to generate a third set of check bits;

(ii) writing the data word into the memory; and

(iii) writing the third set of check bits into the memory so as to associate the third set of check bits with the data word.

3. The method recited in claim 2, wherein the first logical operation is an exclusive-OR operation between the first set of check bits and the second set of check bits and wherein the second logical operation is an exclusive-OR operation between the second set of check bits and a byte write error code.

4. The method recited in claim 2, wherein the codes having a few bits or only one bit different from the byte write error code are uncorrectable error codes to increase the probability of detecting an earlier detected uncorrectable error.

5. The method recited in claim 2, wherein the data word is 64 bits in length and wherein each set of the first, second, and third sets of check bits is 8 bits in length.

6. The method recited in claim 5 wherein the byte write error code is 01111111, wherein the left-most bit is the least significant bit and the right-most bit is the most significant bit.

7. The method recited in claim 6, further comprising the step of

(f) indicating an uncorrectable error if the syndrome corresponds to an error code that indicates an uncorrectable error.

8. A method for error detection comprising the steps of:

(a) reading a data word from a memory;

(b) reading from the memory a first set of check bits associated with the data word read from the memory;

(c) generating a second set of check bits from the data word that has been read from the memory;

(d) performing a logical operation between the first set of check bits and the second set of check bits to generate a syndrome; and

(e) indicating a failed memory operation if the syndrome corresponds to a byte write error code.

9. The method recited in claim 8 further comprising the step of

(f) indicating an uncorrectable error if the syndrome corresponds to an error code that indicates an uncorrectable error.

10. The method recited in claim 9, wherein the byte write error code is surrounded by unused error codes such that the probability is increased that an uncorrectable error will be indicated if more than a single-bit error occurs after a failed memory operation.

11. A method for error detection comprising the steps of:

(a) reading a data word from a memory;

(b) reading from the memory a first set of check bits associated with the data word read from the memory;

(c) generating a second set of check bits from the data word that has been read from the memory;

(d) performing a first logical operation between the first set of check bits and the second set of check bits to generate a syndrome;

(e) decoding the syndrome in order to detect the presence or absence of an uncorrectable error, and upon the detection of an uncorrectable error during a partial write operation,

(i) performing a second logical operation between the second set of check bits and a byte write error code to generate a third set of check bits;

(ii) writing the data word into the memory;

(iii) writing the third set of check bits into the memory so as to associate the third set of check bits with the data word.

12. A method for error detection comprising the steps of:

(a) reading a data word from a memory;

(b) reading from the memory a first set of check bits associated with the data word read from the memory;

(c) generating a second set of check bits from the data word that has been read from the memory;

(d) performing a logical operation between the first set of check bits and the second set of check bits to generate a syndrome;

(e) indicating a failed partial write operation if the syndrome corresponds to a byte write error code.

13. An apparatus for error detection comprising:

(a) means for reading a data word from a memory;

(b) means for reading from the memory a first set of check bits associated with the data word read from the memory;

(c) means for generating a second set of check bits from the data word that has been read from the memory;

(d) means for performing a first logical operation between the first set of check bits and the second set of check bits to generate a syndrome;

(e) means for decoding the syndrome in order to detect the presence or absence of an uncorrectable error;

(f) means for performing, after the detection of an uncorrectable error, a second logical operation between the second set of check bits and a byte write error code to generate a third set of check bits;

(g) means for writing, after the detection of an uncorrectable error, the data word into in the memory;

(h) means for writing, after the detection of an uncorrectable error, the third set of check bits into the memory so as to associate the third set of check bits with the data word.

14. The apparatus recited in claim 13, wherein the first logical operation is an exclusive-OR operation between the first set of check bits and the second set of check bits and wherein the second logical operation is an exclusive-OR logical operation between the second set of check bits and a byte write error code.

15. The apparatus recited in claim 13, wherein the codes having a few bits or only one bit different from the byte write error code are uncorrectable error codes to increase the probability of detecting an earlier detected uncorrectable error.

16. The apparatus recited in claim 13, wherein the data word is 64 bits in length and wherein each set of first, second, and third sets of check bits is 8 bits in length.

17. The apparatus recited in claim 16, wherein the byte write error code is 01111111, wherein the left-most bit is the least significant bit and the right-most bit is the most significant bit.

19. The apparatus recited in claim 14, further comprising:

(f) means for indicating an uncorrectable error if the syndrome corresponds to an error code that indicates an uncorrectable error.

20. The apparatus recited in claim 19, wherein the codes having a few bits or only one bit different from the byte write error code are uncorrectable error codes to increase the probability of detecting an earlier detected uncorrectable error.

18. An apparatus for error detection comprising:

(a) means for reading a data word from a memory;

(b) means for reading from the memory a first set of check bits associated with the data word read from the memory;

(c) means for generating a second set of check bits from the data word that has been read from the memory;

(d) means for performing a logical operation between the first set of check bits and the second set of check bits to generate a syndrome; and

(e) means for indicating a failed memory operation if the syndrome corresponds to a byte write error code.

21. A memory board for use in a data processing system and having error detection capability, comprising:

(a) memory means for storing a plurality of data words;

(b) means for reading a first one of the data words from the memory means;

(c) means for reading form the memory means a first set of check bits associated with the first data word;

(d) means for generating a second set of check bits from the first data word;

(e) means for performing a first logical operation between the first set of check bits and the second set of check bits to generate a syndrome;

(f) means for decoding the syndrome in order to detect the presence of an uncorrectable error;

(g) means for performing, after the detection of an uncorrectable error, a second logical operation between the second set of check bits and a byte write error code to generate a third set of check bits;

(h) means for writing, after the detection of an uncorrectable error, the first data word into the memory means;

(i) means for writing, after the detection of an uncorrectable error, the third set of check bits into the memory means so as to associate the third set of check bits with the first data word.

22. The memory board recited in claim 21, wherein the first logical operation is an exclusive-OR operation between the first set of check bits and the second set of check bits and wherein the second logical operation is an exclusiveOR logical operation between the second set of check bits and a byte write error code.

23. The memory board recited in claim 21, wherein the codes having a few bits or only one bit different from the byte write error code are uncorrectable error codes to increase the probability of detecting an earlier undetected uncorrectable error.

24. The memory board recited in claim 21, wherein the data word is 64 bits in length and wherein each set of first, second, and third sets of check bits is 8 bits in length.

25. The memory board recited in claim 24, wherein the byte write error code is 01111111, wherein the left-most bit is the least significant bit and the right-most bit is the most significant bit.

26. A memory board for use in a data processing system and having error detection capability, comprising:

(a) memory means for storing a plurality of data words;

(b) means for reading a first one of the data words from the memory means;

(c) means for reading from the memory means a first set of check bits associated with the first data word;

(d) means for generating a second set of check bits from the first data word;

(e) means for performing a logical operation between the first set of check bits and the second set of check bits to generate a syndrome;

(f) means for indicating a failed memory operation if the syndrome corresponds to a byte write error. code.

27. The memory board recited in claim 26, further comprising:

(f) means for indicating an uncorrectable error if the syndrome corresponds to an error code that indicates an uncorrectable error.

28. The memory board recited in claim 27, wherein the codes having a few bits or only one bit different from the byte write error code are uncorrectable error codes to increase the probability of detecting an earlier detected uncorrectable error.

29. An error detecting memory system, for use in a data processing system having a data bus,

(a) means for receiving data words from the data bus;

(b) means for generating check bits for each of the received data words;

(c) memory means for storing the received data words and the generated check bits;

(d) means for reading a first one of the data words from the memory means;

(e) means for reading from the memory means a first set of check bits associated with the first data word;

(f) means for generating a second set of check bits from the first data word;

(g) means for performing a first logical operation between the first set of check bits and the second set of check bits to generate a syndrome;

(h) means for decoding the syndrome to detect the presence of an uncorrectable error;

(i) means for performing, after the detection of an uncorrectable error, a second logical operation between the second set of check bits and a byte write error code to generate a third set of check bits;

(j) means for writing, after the detection of an uncorrectable error, the first data word into the memory means;

(k) means for writing, after the detection of an uncorrectable error, the third set of check bits into the memory means so as to associated the third set of check bits with the first data word.

30. The memory system recited in claim 29, further comprising:

(f) means for indicating an uncorrectable error if the syndrome corresponds to an error code that indicates an uncorrectable error.

31. The memory system recited in claim 30, wherein the codes having a few bits or only one bit different from the byte write error code are uncorrectable error codes to increase the probability of detecting an earlier detected uncorrectable error.

32. The memory system recited in claim 29, wherein the first logical operation is an exclusive-OR operation between the first set of check bits and the second set of check bits and wherein the second logical operation is an exclusive-OR logical operation between the second set of check bits and a byte write error code.

33. The memory system recited in claim 29, wherein the codes having a few bits or only one bit different from the byte write error code are uncorrectable error codes to increase the probability of detecting an earlier detected uncorrectable error.

34. The memory system recited in claim 29, wherein the data word is 64 bits in length and wherein each set of first, second, and third sets of check bits is 8 bits in length.

35. The memory system recited in claim 34 wherein the byte write error code is 01111111, wherein the left-most bit is the least significant bit and the right-most bit is the most significant bit.

36. An error detecting memory system, for use in a data processing system having a data bus, comprising:

(a) means for receiving data words from the data bus;

(b) means for generating check bits for each of the received data words;

(c) memory means for storing the received data words and the generated check bits;

(d) means for reading a first one of the data words from the memory means;

(e) means for reading from the memory means a first set of check bits associated with the first data word;

(f) means for generating a second set of check bits from the first data word;

(g) means for performing a logical operation between the first set of check bits and the second set of check bits to generate a syndrome;

(h) means for indicating a failed memory operation if the syndrome corresponds to a byte write error code.