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Signal scrambling transmission system

  • US 4,817,148 A
  • Filed: 07/06/1987
  • Issued: 03/28/1989
  • Est. Priority Date: 07/06/1987
  • Status: Expired due to Fees
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First Claim
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1. A signal scrambling transmission system for transmitting and receiving data comprising:

  • a. a transmitter comprising;

    i. data holding means having a data holding input for accepting data and a data holding output;

    ii. a clock multiplier having a multiplier clock input and a multiplier clock output wherein a system clock signal is received on the multiplier clock input and a second clock signal wherein the second clock signal has a higher frequency than the system clock signal, is generated at the multiplier clock output, and the system clock signal clocks the data into the data holding means and the second clock signal is used to clock the data out at a faster rate;

    iii. an addressable transmitter memory having a transmitter memory address input and a transmitter memory sequence output wherein the transmitter memory is divided into a number of frames each having a frame length which includes a known synchronization word having a synchronization word length, a frame index word for identifying the frames and having an index word length, and a pseudo random sequence of bits having a pseudo random sequence length wherein the sum of the synchronization word length and the index word length is less than two percent of the frame length;

    iv. a transmitter address counter having a transmitter counter input connected to the multiplier clock output for receiving the second clock signal and generating an address on an address output including the index word wherein the address is connected to the transmitter memory via its address input for identifying the location of the pseudo random sequence that is being output on the sequence output of the transmitter memory; and

    v. logic scrambler means connected to the sequence output of the transmitter memory and to the data holding output for logically combining the data, the pseudo random sequence, the synchronization word, and the index word in timed relationship to produce scrambled data at a scrambled data output;

    b. a transmission medium connected to the scrambled data output for conveying the scrambled data to a remote location;

    c. a receiver comprising;

    i. scrambled data holding means having a scrambled data holding input connected to the transmission medium for receiving a scrambled data and a scrambled data holding output;

    ii. clock recovery means connected via a recovery clock input to the transmission medium for recovering the second clock signal and generating the system clock signal on a recovery clock output therefrom wherein the second clock signal is used to clock the scrambled data into the scrambled data holding means;

    iii. detection means connected to the scrambled data holding output for detecting the synchronization word and the index word in the scrambled data and producing a synchronization signal on a first detector output upon detection of the synchronization word and outputting the index word corresponding to the detected synchronization word on a second detector output;

    iv. an addressable receiver memory having a receiver memory address input and a receiver memory sequence output, wherein the receiver memory is divided into the same number of frames as the transmitter memory and each frame includes the same pseudo random sequence of bits as the transmitter memory;

    v. a receiver address counter having a receiver counter input connected to the recovery clock input for receiving the fast clock signal, to the first detector output for receiving the synchronization signal, and to the second detector output for receiving the index word and producing an address count including the index word and having a receiver counter output connected to the receiver memory address input for identifying the location of the pseudo random sequence that is being output on the receiver memory sequence output; and

    vi. logic descrambler means connected to the sequence output of the receiver memory and the scrambled data holding output for combining the pseudo random sequence with the scrambled data to recover the data.

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