Video stream processing system

• US 4,817,175 A
• Filed: 05/04/1987
• Issued: 03/28/1989
• Est. Priority Date: 08/26/1986
• Status: Expired due to Fees

• Current Assignee: Schlumberger Systems & Services Incorporated
• Original Assignee: Schlumberger Systems & Services Incorporated
• Inventors: Tenenbaum, Jay M., Deering, Michael F.
• Primary Examiner(s): Boudreau, Leo H.
• Assistant Examiner(s): Couso, Jose L.
• Application Number:
  US07/048,488
• Time in Patent Office: 694 Days
• Field of Search: 358/21 R, 358/22, 358/139, 358/140, 358/903, 382/41, 382/47, 382/49, 382/50, 382/52
• US Class Current: 382/303
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 5/20 using local operators
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A video stream processing system comprising a novel modular family of image processing and pattern recognition submodules, the submodules utilize a unique system signalling and interface protocol, and thus can be cascaded and paralleled to produce complex special purpose image processing systems which can operate at video or near video data rates. A stream of digitized pixel data is pipelined through a variety of submodules to support a wide variety of image processing applications. A common video interface provides for handling pixel data in the video signal path and a processor interface allows communication to any modern microprocessor for overall system control, for optional addition image processing and for defining options within each submodule.

Claims

1. A video signal processing system comprising:

means for coupling to a video signal source of pixel data;

a modular family of vision processing subsystems, each modular subsystem having a standard processor interface and a standard video input interface, at least one of said modular subsystems having a video output interface for coupling to a video input interface of another modular subsystem or an output of said video signal processing system, a plurality of said subsystems being different, special purpose subsystems permanently configured to perform different operations on said pixel data, including

frame buffer means for selectively storing and retrieving said pixel data in a read/write memory and communicating said pixel data between said read/write memory and said video input interface,

histogram means for outputting characteristic data representative of statistic analysis of said pixel data responsive to signals on said processor interface,

look-up table means for functionally mapping from pixel data, as input through said video input interface, to characteristic data for output as pixel data through said video output interface,

filter means for constructing an N×

M window of pixel data and providing characteristic data on said N×

M window, and

delay means having M storage units and providing for selective shifting of pixel data unidirectionally relative to the M storage units of said delay means so as to effect a temporal delay of M shift times;

a pipeline pixel bus coupling in series said means for coupling to a video signal source and a plurality of said video input interfaces and providing a valid pixel synchronization signal, a line synchronization signal, a frame synchronization signal, and pixel data; and

a processor bus coupled to each said standard processor interface.

2. The system of claim 1 wherein a plurality of said modular subsystems each further comprises a custom memory interface.

3. The system of claim 1 further comprising a plurality of memories, each said memory being coupled to one of said plurality of said modular subsystems.

4. The system of claim 1 further comprising means for multiplexing addresses and data on said processor bus.

5. The system of claim 1 wherein said pixel data is in raster scan format.

6. The system of claim 1 wherein said pixel bus and said processor bus are asynchronous with respect to each other.

7. The system of claim 1 further comprising a plurality of processor interface select lines, each of said select lines being coupled to one of said standard processor interfaces.

8. The system of claim 1 further comprising a processor coupled to said processor bus.

9. The system of claim 1 wherein said processor interface includes a select line, a transfer delay line and multiplexed data and address lines.

10. The system as in claim wherein said delay means is further comprised of

a plurality of N delay means, including first and last delay means,

each delay means having M storage units, each delay means providing for selective shifting the addressing of pixel data unidirectionally relative to the M storage units of said delay means so as to effect a temporal delay of M shift times,

the input of said first delay means coupled to receive the output pixel data from the video interface of one of said plurality of subsystems,

the output of each said N delay means coupling to a separate one of N video interface inputs of a second one of said plurality of subsystems having N video interfaces.

the outputs of all but the last delay means coupling to the input of a next delay means,

wherein said plurality of N delay means provides N temporally staggered streams of M units of pixel data output to said second subsystem.