Concurrent memory access system

• US 4,818,932 A
• Filed: 07/05/1988
• Issued: 04/04/1989
• Est. Priority Date: 09/25/1986
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Odenheimer, Ronald P.
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): BURNS, WILLIAM
• Application Number:
  US07/214,790
• Time in Patent Office: 273 Days
• Field of Search: 324/121 R, 324/73 R, 340/722, 340/728, 340/798, 340/799, 340/747, 364/200, 364/900
• US Class Current: 324/121.00R
• CPC Class Codes: G01R 13/345 for displaying sampled signals by using digital processors by intermediate A.D. and D.A. convertors (control circuits for CRT indicators)
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/1647 with interleaved bank access

Abstract

A system for providing concurrent access to an addressable memory space by a plurality of data processing devices includes a plurality of independently accessible memory banks, each memory bank providing a separate portion of the addressable memory space. A memory management unit includes address and data multiplexers corresponding to each memory bank for providing access by any selected one of the data processing devices to the corresponding memory bank and also includes circuits for controlling the multiplexers to permit different processing devices to access different memory banks at the same time while arbitrating competing demands for the same memory bank.

Claims

1. A system for providing concurrent access to an addressable memory space having consecutive memory addresses by a plurality of data processing devices, comprising:

N independently accessible memory banks, each memory bank providing a separate portion of said addressable memory space, wherein each separate portion of said addressable space consists of every Nth one of said consecutive memory addresses and N is an integer having a value greater than one;

port means for communicating with said data processing devices for providing a memory bank address for each memory bank access by each data processing device, and for generating indicating signals indicating which of said memory banks each data processing device is to access in accordance with a value of the memory bank address provided;

a plurality of address multiplexing means, each corresponding to a separate one of said memory banks, and each for providing an address for accessing the corresponding memory bank, the address being selected from among said addresses provided by said port means;

a plurality of data multiplexing means, each corresponding to a separate one of said memory banks, and each for completing a data path between the corresponding memory bank and any selected one of said data processing device; and

controller means for generating control signals for controlling the operation of each memory bank during each memory bank access and for controlling each address multiplexing means and each data multiplexing means according to said indicating signals generated by said port means.

2. The system according to claim 1 wherein said controller means comprises arbitration means responsive to said indicating signals for determining which of said data processing devices is to access each memory bank at any given time.

3. The system according to claim 1 wherein said port means includes a sequential address generator for generating a sequence of said memory bank addresses, said sequential address generator comprising:

means for storing a base address;

means for maintaining a count of the number of times said memory banks are addressed by a memory address of said sequence of memory bank addresses; and

means for adding said base address to said count to generate each memory bank address of said sequence of memory bank addresses.

4. A digital oscilloscope comprising:

N independently accessible memory banks, each memory bank for providing a separate portion of an addressable memory space having consecutive memory addresses, wherein each separate portion of said addressable space consists of every Nth one of said consecutive memory addresses and N is an integer having a value greater than one;

digitizer means for producing a sequence of sampled waveform data to be stored in said addressable memory space;

processing means for generating a sequence of processed waveform data to be stored in said addressable memory space; and

memory management means for providing random access to any one of said memory banks for said digitizer means while providing concurrent random access to any other of said memory banks for said processing means so that the sequence of sampled waveform data occurs in consecutive memory addresses of the addressable memory space.

5. A digital oscilloscope comprising:

N independently accessible memory banks, each memory bank providing a separate portion of an addressable memory space, wherein each separate portion of said addressable space consists of every Nth one of said consecutive memory addresses and N is an integer having a value greater than one;

digitizer means for producing a sequence of sampled waveform data to be stored in said addressable memory space;

a screen for displaying waveform images;

display controller means for displaying waveform images on said screen based on sampled waveform data sequences stored in said addressable memory space on said screen; and

memory management means for providing random access to one of said memory banks for one of said digitizer and display controller means while providing concurrent random access to any other of said memory banks for the other of said digitizer and display controller means so that the sequence of sampled waveform data occurs in consecutive memory addresses of the addressable memory space.

6. The digital oscilloscope according to claim 5 wherein said memory management means comprises:

port means for communicating with said digitizer and display controller means, for providing a memory bank address for each memory bank access by each of said digitizer and display controller means, and for generating indicating signals indicating which of said memory banks each of said digitizer and display controller means is to access in accordance with a value of the memory bank address provided;

a plurality of address multiplexing means, each corresponding to a separate one of said memory banks, and each for providing an address for accessing the corresponding memory bank, the address being selected from among said addresses provided by said port means;

a plurality of data multiplexing means, each corresponding to a separate one of said memory banks, and each for completing a data path between the corresponding memory bank and any selected one of said digitizer and display controller means; and

controller means for generating control signals for controlling the operation of each memory bank during each memory bank access and for controlling each address multiplexing means and each data multiplexing means according to said indicating signals generated by said port means.

7. The digital oscilloscope according to claim 6 wherein said port means includes a sequential address generator for generating a sequence of said memory bank addresses, said sequential address generator comprising:

means for storing a base address;

means for maintaining a count of the number of times said memory banks are addressed by a memory address of said sequence of memory bank addresses; and

means for adding said base address to said count to generate each memory bank address of said sequence of memory bank addresses.

8. An improved digital oscilloscope of the type having a digitizer for converting an input analog signal to digital data words, a waveform memory to store the digital data words, and a display controller for displaying the digital data from the waveform memory on a display, all under control of a microprocessor, wherein the improvement comprises:

means for addressing the waveform memory as a plurality of memory banks;

means for accessing each memory bank simultaneously by at least two processing units taken from the set including the digitizer, the microprocessor and the display controller; and

means for alternating data accesses to the memory banks between each of the processing units so that the data for each processing unit occurs in sequential data addresses of the waveform memory.

9. An improved digital oscilloscope as recited in claim 8 further comprising means for arbitrating between the processing units when more than one processing unit seeks to access the same memory bank.