Merged bipolar/CMOS technology using electrically active trench

• US 4,819,052 A
• Filed: 12/22/1986
• Issued: 04/04/1989
• Est. Priority Date: 12/22/1986
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hutter, Louis N.
• Primary Examiner(s): Macon, Robert S.
• Application Number:
  US06/945,796
• Time in Patent Office: 834 Days
• Field of Search: 357/49, 357/71, 357/34, 357/41, 357/55
• US Class Current: 257/378
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors

Abstract

Disclosed is a structure and method of fabricating bipolar and MOSFET devices isolated by an electrically active trench. A doped epitaxial layer (24) is formed on semiconductor substrate (10). A trench (36) is formed through the epitaxial layer (24) down to the substrate (10). The trench (36) is filled with a conductive material (54) and a topside contact (182) is formed in electrical contact with the conductive trench. A bipolar transistor (176) is formed in the epitaxial area (38) on one side of the trench (36) and a MOSFET transistor (178) is formed in the epitaxial area (40) on the other side of the trench (36). Plural contacts (200-206) can be made to the top surface of the trench (186), thereby maintaining the underlying substrate (10) at a desired and uniform potential.

Claims

1. A semiconductor circuit comprising:

a conductive substrate of a first conductivity type material;

first and second semiconductor areas of a second conductivity type material formed on said substrate;

a trench separating said first and second semiconductor areas, said trench including electrically isolating sidewalls and a bottom formed in said substrate;

a conductive material filling said trench and in electrical contact with said substrate; and

first and second semiconductor devices formed in respective said first and second semiconductor areas.

2. The semiconductor circuit of claim 1 wherein said trench sidewalls include electrical isolation comprising silicon nitride and silicon oxide.

3. The semiconductor circuit of claim 1 wherein said trench conductive material is doped with an impurity of said first conductivity type.

4. The semiconductor circuit of claim 1 wherein one of said semiconductor devices comprises a bipolar transistor and another of said semiconductor devices comprises a field effect transistor.

5. The semiconductor circuit of claim 4 further including a contact electrode formed in electrical contact with said conductive material filling said trench, and said electrode is connected to a ground node of said semiconductor circuit.

6. The semiconductor circuit of claim 1 further including a contact electrode formed in electrical contact with said conductivity material of said trench.

7. The semiconductor circuit of claim 6 further including a reference ground terminal of said semiconductor circuit, and wherein said contact electrode is connected to said ground terminal.

8. The semiconductor circuit of claim 1 wherein said trench is formed in a matrix enclosing a plurality of semiconductor areas.

9. The semiconductor circuit of claim 8 further including a plurality of electrical connections to the conductive material of said trench, said electrical connections being located on a trench surface opposite the connection thereto by said substrate.

10. A method of fabricating a semiconductor circuit with a bipolar transistor isolated from a MOSFET transistor, comprising the steps of:

forming a layer of semiconductor material of a first conductivity type on a substrate of second conductivity type;

forming a trench through said layer of semiconductor material into contact with said substrate;

forming an electrical isolation adjacent the sidewalls of said trench;

filling said trench with a conductive material of said second conductivity type; and

forming a bipolar transistor and a MOSFET transistor in said layer of semiconductor material, each said transistor formed on opposing sides of said trench.

11. The method of claim 10 further including forming a heavily doped buried layer of semiconductor material underlying said transistors and disposed between said layer of semiconductor material and said substrate.

12. The method of claim 10 further including forming said transistors with respective semiconductor regions contiguous with the sidewalls of said trench.

13. The method of claim 10 further including forming a semiconductor well of said second conductivity type in said layer of semiconductor material, and forming said MOSFET transistor in said semiconductor well.

14. The method claim 10 further including forming an external electrical contact to said conductive material of said trench.

15. The method of claim 14 further including forming a plurality of electrical contacts to said conductive material.

16. The method of claim 14 further including forming one of said transistor for carrying large currents, and forming said electrical contact to said trench proximate said transistor carrying large currents.

17. A semiconductor structure formed according to the method of claim 10.

18. A method of providing multiple contacts to a substrate of a semiconductor circuit, comprising:

forming a layer of semiconductor material on said substrate;

forming a trench matrix through said semiconductor material into contact with said substrate;

filling said trench matrix with a conductive material which is in electrical contact with said substrate; and

forming a plurality of electrical contacts to said conductive material at locations remote from said substrate.

19. The method of claim 18 and further including connecting each said electrical contact together, in order to reduce debiasing effects.

20. The method of claim 19 and further including connecting said plurality of contacts to a ground node.

21. The method of claim 18 and further including isolating said conductive material filling said trench matrix from said semiconductor material.

22. The method claim 21 and further including forming two transistor devices in said conductive material and isolated from one another by said trench matrix.