Phase comparator for extending capture range

• US 4,819,081 A
• Filed: 09/03/1987
• Issued: 04/04/1989
• Est. Priority Date: 09/03/1987
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Baucom, Terry L., Volk, Andrew M., Van Brunt, Roger
• Primary Examiner(s): Laroche, Eugene R.
• Assistant Examiner(s): Ham, Seung
• Application Number:
  US07/092,477
• Time in Patent Office: 579 Days
• Field of Search: 328/155, 328/133, 328/134, 328/63, 328/72, 307/514, 307/516, 307/119, 307/120, 331/25, 331/10, 331/11, 331/1 A, 331/DIG. 2, 375/119, 375/120
• US Class Current: 327/12
• CPC Class Codes: H03D 13/004 the logic means delivering pulses at more than one terminal, e.g. up and down pulses
• CPC Class Codes: H03L 7/1072 by changing characteristics of the charge pump, e.g. changing the gain

Abstract

An extended range logic circuit is activated to decrease the settling time and prevent slip, when phase difference of two signals being compared by a phase comparator reaches a slip point. The circuit provides error correction signals to compensate for the phase correction at a much faster rate when the phase error reaches a predetermined point, which is proximate to the slip point. However, the extended capture range circuit in only active during the lock acquisition. After lock is achieved the extended capture range logic is disabled, to provide better jitter performance.

Claims

1. In a phase comparator having a first input signal, a second input signal, a first correction output signal that indicates error correction in a first direction, and a second correction output signal that indicates error correction a in second direction that is opposite to the first direction, an extended range logic circuit comprising:

means for generating a slip signal that indicates that a phase difference between the first input signal of the comparator and the second input signal of the comparator has reached a predetermined value;

means for generating a direction signal that indicates the direction of the phase difference between the first input signal of the comparator and the second input signal of the comparator;

means responsive to the direction signal, the slip signal, and an enable signal for generating an acceleration signal that indicates error correction in a first direction and for generating a brake signal that indicates error correction in a second direction that is opposite from the first direction, wherein the acceleration and brake signals are updated only during non-slip periods;

means responsive to the slip signal, the acceleration signal, and the brake signal for generating a third correction output signal that indicates error correction in a first direction and for generating a fourth correction output signal that indicates error correction in a second direction that is opposite from the first direction; and

means responsive to the first, second, third, and fourth correction output signals for selecting one among the first, second, third, and fourth correction outputs signals, wherein the first and second correction output signals provide error correction at a first rate and the third and fourth correction output signals provide error correction at a second rate that is faster than the first rate,

whereby a more rapid error correction is achieved when the phase difference between the first input signal of the comparator and the second input signal of the comparator reaches the predetermined value.

2. In a phase comparator having a first input signal, a second input signal, a first correction output signal that indicates error correction in a first direction, and a second correction output signal that indicates error correction in a second direction that is opposite to the first direction, an extended range logic circuit comprising:

a first flip-flop having an input that is a pulse of a predetermined duration generated whenever a data pulse is encountered, the first flip-flop being clocked by the first input signal of the comparator;

a second flip-flop having an input coupled to an output of the first flip-flop, the second flip-flop being clocked by the first input signal of the comparator;

a logic gate having a first input coupled to the output of the first flip-flop, a second input coupled to an output of the second flip-flop, and an output that is a slip signal that indicates that a phase difference between the first input signal of the comparator and the second input signal of the comparator has reached a predetermined value;

a third flip-flop which is clocked by the second input signal of the comparator;

a fourth flip-flop which is clocked by the first input signal of the comparator and which has an input that is coupled to a first output of the third flip-flop and an output that is coupled to an input of the third flip-flop, wherein a second output of the third flip-flop is a direction signal that indicates the direction of the phase difference between the first input signal of the comparator and the second input signal of the comparator;

a fifth flip-flop having an input coupled to the second output of the third flip-flop and having a first output that is an acceleration signal that indicates error correction in a first direction and a second output that is a brake signal that indicates error correction in a second direction that is opposite from the first direction; and

a logic circuit having the slip signal, the acceleration signal, and the brake signal as inputs, having a first output that is a third correction signal that indicates error correction in a first direction, and, additionally, having a second output that is a fourth correction signal that indicates error correction in a second direction that is opposite from the first direction,

whereby a more rapid error correction is achieved when the phase difference between the first input signal of the comparator and the second input signal of the comparator reaches the predetermined value.

3. The extended range logic circuit of the phase comparator of claim 2, further comprising:

means responsive to the slip signal, the pulse applied as an input to the first flip-flop, and an enable signal for generating an update signal that allows the acceleration and brake signals of the fifth flip-flop to be updated only during non-slip periods.

4. The extended range logic circuit of the phase comparator of claim 2, wherein the first input signal of the comparator is a feedback signal and the second input signal of the comparator is a clock signal.