Sampled data subsampling apparatus

• US 4,819,252 A
• Filed: 02/16/1988
• Issued: 04/04/1989
• Est. Priority Date: 02/16/1988
• Status: Expired due to Term

• Current Assignee: RCA Licensing Corporation
• Original Assignee: Thomson Consumer Electronics Incorporated (Vantiva SA)
• Inventors: Christopher, Todd J.
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US07/155,944
• Time in Patent Office: 413 Days
• Field of Search: 375/25, 375/26, 375/27, 375/30, 375/96, 375/122, 375/103, 364/724, 364/825, 381/29-31
• US Class Current: 375/240
• CPC Class Codes: H03H 17/0664 where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation

Abstract

An antialias filtering and subsampling system incorporates a compound accumulator including three cascade connected accumulator circuits conditioned to integrate and dump the integrated values of n input samples. The integrated values from the three integrators are scaled, delayed and combined to produce substampled values of a signal which has been filtered according to the transfer function [sin(nπft)/nsin(πft)]³.

Claims

1. Apparatus for filtering and subsampling a sample data signal occurring at a first rate f_s to produce samples at a second rate f_s /n, n an integer, said apparatus comprising:

an input terminal for receiving said sampled data input signal;

a compound accumulator, coupled to said input terminal, for providing first output values corresponding to the accumulated values of successive input samples of exclusive groups of n input samples of said input signal, second output values corresponding to a double accumulation of values of successive input samples of said exclusive groups of n input samples, and third output values corresponding to a triple accumulation of values of successive input samples of said exclusive groups of n input samples;

first means coupled to said compound accumulator for combining said first, second and third output values in the ratio n(n-1)/2;

-n;

1 to produce a first combined signal FCS1;

second means coupled to said compound accumulator for combining said first, second and third output values in the ratio n(n+1)/2;

n;

-2 to produce a second combined signal FCS2;

third means coupled to said compound accumulator and to said first and second means, for providing said signal FSC2 delayed by one subsample period and said signal FCS1 delayed by two subsample periods, and for combining said third output values with said signal FCS2 delayed by one subsample period and said signal FCS1 delayed by two subsample period.

2. The apparatus set forth in claim 1 wherein aid compound accumulator comprises the cascade connection of three accumulator circuits.

3. The apparatus set forth in claim 2 wherein said third means comprises:

first delay means, coupled for receiving said signal FCS1, for delaying signal FCS1 by a period of n/f_s seconds;

summing means, coupled to said first delay means, for combining delayed representations of signal FCS1 with signal FCS2;

second delay means, coupled to said summing means, for delaying signal provided by said summing means by a period of n/f_s seconds;

further summing means coupled to said second delay means and said compound accumulator for combining said third output values with delayed signal provided by said second delay means.

4. The apparatus set forth in claim 1 wherein said third means comprises:

first delay means, coupled for receiving said signal FCS1, for delaying signal FCS1 by a period of n/f_s seconds;

summing means, coupled to said first delay means, for combining delayed representations of signal FCS1 with signal FCS2;

second delay means, coupled to said summing means, for delaying signal provided by said summing means by a period of n/f_s seconds;

further summing means coupled to said second delay means and said compound accumulator for combining said third output values with delayed signal provided by said second delay means.

5. Apparatus for filtering and subsampling a sampled data signal occurring at a sample rate f_s, to produce samples at a rate f_s /n where n is an integer, said apparatus comprising:

an input terminal for receiving said sampled data signal;

a cascade connection of first, second and third accumulators, said first accumulator being coupled to said input terminal for providing first intermediate accumulated values of successive input samples and providing first accumulated output values corresponding to the accumulated values of successive input samples in exclusive groups of n successive samples, said second accumulator being coupled to said first accumulator for providing second intermediate accumulated values of said first intermediate accumulated values and for providing second accumulated output values corresponding to the accumulated value of successive first intermediate accumulated values over each exclusive group of n samples, and said third accumulator being coupled to said second accumulator for providing third accumulated output values corresponding to the accumulated value of successive second intermediate accumulated values over each exclusive group of n samples;

first means coupled to said first, second and third accumulators for combining said first, second and third accumulated output values in the ratio n(n-1)/2;

-n;

1 to generate a first combined signal FCS1;

second means coupled to said first, second and third accumulators for combining said first, second and third accumulated output values in the ratio n(n+1)/2;

n;

-2 to generate a second combined signal FCS2;

third means coupled to said first and second means and said third accumulator for combining said third accumulated output signal, and said signals FCS1 and FCS2 to produce a filtered, subsampled signal.

6. The apparatus set forth in claim 5 wherein said third means comprises means for providing said signal FCS2 and FCS1 delayed by one and two subsample periods respectively and, for combining said third accumulated output value with said signal FCS2 delayed by one subsample period and with said signal FCS1 delayed by two subsample periods.

7. Bit-serial apparatus for filtering a sampled data signal, including an accumulator comprising:

sampled data input port for receiving said sampled data signal, and a serial output port;

a plurality of adder circuits each having carry-input, carry-output, addend input, augend input and sum data terminals, and including means for selectively coupling said sum data terminal or a reference value to said augend input terminal;

means for connecting N, an integer, of said adder circuits in parallel wherein said adder circuits are ordinally numbered one to N, the carry input terminal of adder circuit numbered one being coupled to a reference value and the carry output terminal of each adder circuit being connected to the carry-input terminal of the next higher ordinally numbered adder circuit, the addend input terminal of at least adder circuit numbered one being coupled to said sampled data input port, and the addend input terminals of adder circuits which are not coupled to said sampled data input port being coupled to a reference value; and

means for successively coupling in the order of ordinal numbering of adder circuits, the respective sum data terminals to said serial output port.

8. The bit-serial apparatus set forth in claim 7 wherein said accumulator further includes

means for connecting M of said adder circuits in parallel, M an integer greater than N, wherein said M adder circuits are ordinally numbered one to M, the carry input connection of adder circuit numbered one being coupled to a reference value and the carry output connection of each adder circuit being connected to the carry input connection of the next higher ordinally numbered adder circuit, the addend input connections of the first N of the M parallel connected adder circuits beng coupled to the sum data terminals of the N parallel connected adder circuits according to their corresponding ordinal numbering, the addend input connections of the remaining M parallel connected adder circuits which are not connected to the sum data output terminals of the N parallel connected adder circuits being respectively connected to a reference value;

a further serial output port; and

means for successively coupling in the order of ordinal numbering of adder circuits, the respective sum data terminals to said further serial output port.

9. Bit-serial apparatus for filtering a sampled data signal, including an accumulator comprising;

an input port for receiving said sampled data signal;

a plurality of adder circuits, each of said adder circuits being a one-bit adder having carry-input, carry-output, addend input, augend input, data output, strobe input and strobed data output terminals, said adder providing a carry output signal to said carry output terminal and a sum output signal to said data output terminals, said adder circuit further including first and second gating means having respective control input connections coupled to said strobe input terminal, and having respective input terminals coupled to receive said sum output signal, said first gating means coupled said sum output signal to said strobed data output terminal responsive to a first state of a strobe signal and exhibiting high impedance responsive to a second state of said strobe signal, said second gating means coupled said sum output signal to said augend input terminal responsive to said second state of said strobe signal and coupling a zero value to said augend input terminal responsive to said first state of said strobe signal,

means for connecting N (an integer) of said adder circuits in parallel wherein said adder circuits are ordinally numbered one to N, the carry input terminal of adder circuit numbered one being connected to a logical zero value and the carry output terminal of each adder circuit being connected to the carry input terminal of the next higher ordinally numbered adder circuit, the strobed data output terminals being coupled to a first common output bus, the addend input terminal of at least one of said N adder circuits being coupled to said input port and the addend input terminals of the remaining adder circuits, which are not connected to said input port, being coupled to a logical zero value; and

means for generating a plurality of bistate signals, coupled to respective strobe input terminals of said adder circuits for successively strobing said adder circuits in ascending order of their ordinal numbering.

10. The bit-serial apparatus set forth in claim 9 wherein said accumulator further includes

means for connecting M of said adder circuits in parallel, M an integer greater than N, wherein said M adder circuits are ordinally numbered one to M, the carry input terminal of adder circuit numbered one being coupled to a logical zero value and the carry output terminal of each adder circuit being connected to the carry input terminal of the next higher ordinally numbered adder circuit, the strobed data output terminals being coupled to a second common output bus, the addend input terminals of the first N of the M parallel connected adder circuits being coupled to the data output terminals of the N parallel connected adder circuits according to their corresponding ordinal numbering, the addend input terminals of the remaining M parallel connected adder circuits which are not connected to the data output terminals of the N parallel connected adder circuits being respectively connected to a logical zero value, and

means for coupling the strobe terminals of said M parallel connected adder circuits to said means for generating a plurality of bi-state signals such that said M parallel connected adder circuits are strobed in ascending order of their ordinal numbering.

11. The bit-serial apparatus set forth in claim 9 wherein each of said adder circuits further includes:

means for providing a delay of one input sample period to said sum output signal coupled to said second gating means; and

means for providing a delay of one input sample period to said carry output signal coupled to said carry output terminal.

12. Bit-serial apparatus for filtering a sampled data signal, including an accumulator comprising:

a signal input port for receiving said sampled data signal;

a plurality of single bit accumulators, each of said single bit accumulators having data input, carry input, strobe input, carry output and strobed data output terminals;

means for connecting N (an integer) of said single bit accumulators in parallel wherein said single bit accumulators are ordinally numbered one to N, the carry input terminal of single bit accumulator numbered one being coupled to a logical zero value and the carry output terminal of each single bit accumulator being coupled to the carry input terminal of the next higher ordinally numbered single bit accumulator, the data input terminal of at least one of said N single bit accumulators being coupled to said signal input port and the data input terminals of the remaining single bit accumulators, which are not connected to said signal input port, being coupled to a logical zero value; and

means, coupled to said strobe input terminals of said N single bit accumulators, for conditioning said N single bit accumulators to sequentially provide single bit accumulated output data at their respective strobed data output terminals, in a sequence corresponding to an ascending order of their ordinal numbering, a sequence of N single bit accumulated output data from said N single bit accumlators constituting a bit-serial accumulated sample.