Integrated CMOS circuit comprising a substrate bias voltage generator

• US 4,820,936 A
• Filed: 09/08/1987
• Issued: 04/11/1989
• Est. Priority Date: 05/29/1987
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Van Der Sanden, Cornelis G. L. M., Slob, Arie, Veendrick, Hendrikus J. M.
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Bertelson, David R.
• Application Number:
  US07/094,363
• Time in Patent Office: 581 Days
• Field of Search: 307/296.2, 307/296.8, 307/304, 307/592, 307/475
• US Class Current: 327/534
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: H03K 3/0315 Ring oscillators

Abstract

In CMOS integrated circuits, "latch-up" problems may arise if no special steps are taken. One way to counteract a "latch-up" state is to apply a substrate bias voltage. In an integrated circuit, an externally-clocked substrate bias voltage pump and a stand-by bias voltage generator are provided, the latter not being switched on until the substrate bias voltage becomes less negative than, for example, -2V. As a result, the integrated circuit becomes less sensitive to "latch-up", especially during measuring and testing procedures, in which no external clock signal is supplied.

Claims

1. An integrated CMOS circuit comprising a first substrate bias voltage generator, which can be driven by an external clock generator, which also controls further circuits in the integrated circuit, and a second substrate bias voltage generator, characterized in that said second substrate bias voltage generator comprises a substrate bias voltage pump for generating a substrate bias voltage, an integrated oscillator for driving said substrate bias voltage pump, switching means for switching said oscillator on and off, and a comparator circuit for comparing the substrate bias voltage with a reference voltage and providing an output to drive said switching means.

2. An integrated CMOS circuit as claimed in claim 1, characterized in that the integrated oscillator is a ring oscillator comprising a plurality of series-connected inverter stages, an inverter stage together with the switching means comprising a NOR gate.

3. An integrated CMOS circuit as claimed in claim 1 or 2, characterized in that the comparator circuit comprises an inverter and a series-connected combination of a PMOS transistor, an NMOS transistor and a second PMOS transistor connected as a diode coupled between the positive supply voltage and the substrate voltage, the first-mentioned PMOS and the NMOS transistor being connected by their gate electrodes to ground, a junction point of their drains being connected to the input of the inverter and the diode-connected second PMOS transistor being connected between the NMOS transistor and the substrate voltage.

4. An integrated CMOS circuit comprising a substrate and a substrate bias voltage generator, which includes a first junction point and an oscillator having an output, a capacitance coupled between said first junction point and said output, a first NMOS transistor connected as a diode between the first junction point and ground and a second NMOS transistor connected as a diode between the first junction point and the substrate, characterized in that the width/length ratio of the second transistor is substantially larger than the width/length ratio of the first transistor.

5. An integrated CMOS circuit as claimed in claim 4, characterized in that the width/length ratio of the second transistor exceeds that of the first transistor by a factor 5.