Compensated current sensing circuit

• US 4,820,968 A
• Filed: 07/27/1988
• Issued: 04/11/1989
• Est. Priority Date: 07/27/1988
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Wrathall, Robert S.
• Primary Examiner(s): Wong, Peter S.
• Application Number:
  US07/224,636
• Time in Patent Office: 258 Days
• Field of Search: 323/311, 323/312, 323/313, 323/314, 323/315, 323/316, 330/257, 330/277, 330/288
• US Class Current: 323/316
• CPC Class Codes: G01R 17/06 Automatic balancing arrangements
• CPC Class Codes: G01R 19/16519 using FET's
• CPC Class Codes: G05F 3/24 wherein the transistors are of the field-effect type only G05F3/205, G05F3/26, G05F3/30 take precedence

Abstract

A current sensing circuit includes a first reference resistor connected in series with the source-drain path of a current mirroring transistor across the source-drain path of a power transistor which is N times the size of the current mirroring transistor. Due to the first reference resistor, the current in the mirroring transistor is less than l/N the current in the power transistor. To sense the current in the power transistor more accurately, the current sensing circuitry includes a reference circuit in which the source-drain path of a compensating transistor, of like size as the current mirroring transistor, is connected in parallel with a second reference resistor to produce a reference current which is approximately equal to l/N the current flowing in the power transistor.

Claims

1. The combination comprising:

a. first and second power terminals for the application therebetween of an operating potential;

b. means for connecting a load between said first power terminal and a first node;

c. a first semiconductor switch having its main conduction path connected between said first node and said second power terminal for controlling the current flow through said load;

d. means for sensing the current flowing through said load and said first semiconductor switch comprising;

(i) a second semiconductor switch having its main conduction path connected between said first node and a second node; and

(ii) a first impedance means connected between said second node and said second power terminal; and

e. a reference circuit for producing a current which is proportional to the current flowing through said load comprising;

(i) a current reference generating circuit connected between point of operating potential and a third node;

(ii) a second impedance means connected between said third node and said second power terminal; and

(iii) a third semiconductor switch having its main conduction path connected in parallel with said second impedance means between said third node and said second power terminal.

2. The combination as claimed in claim 1 wherein each one of said first, second and third transistors is a field-effect transistor, having a source-to-drain conduction path defining the main conduction path of each transistor and a control electrode for controlling the conductivity of its source-to-drain conduction path,

wherein the geometry of said second transistor is similar to the geometry of said third transistor, whereby for like bias condition across gate-to-source and drain-to-source the effective impedance of their source-to-drain path is approximately equal;

and

wherein the geometry of said first transistor is "N" times the geometry of said second transistor, whereby for like bias conditions across the gate-to-source and drain-to-source the effective impedance of the source-to-drain path of the first transistor is 1/N times the effective impedance of the second transistor.

3. The combination as claimed in claim 2 wherein the same control potential is applied to the control electrodes of said first, second and third transistors.

4. The combination as claimed in claim 3, wherein the impedance of said first impedance means is equal to the impedance of said second impedance means.

5. The combination as claimed in claim 4 further including a comparator having first and second inputs,

wherein said second node is connected to said first input of said comparator, and wherein said third node is connected to said second input of said comparator.

6. In combination with a circuit in which the conduction path of a first power transistor is connected between an output terminal and a point of reference potential, and in which the conduction path of a second sensing transistor is connected in series with a current sensing resistor across the conduction path of the first power transistor, and wherein the geometry of the sensing transistor is designed to be 1/N times the geometry of the first power transistor in order to carry 1/N times the current flowing in the power transistor, but wherein due to the presence of the current sensing resistor the current flowing through the sensing transistor is offset, being less than 1/N times the current through the first power transistor, an improved reference circuit for producing a compensated reference current which is more nearly proportional to the current in said power transistor comprising:

a current source for applying a current into a node;

a reference resistor having the same value as said current sensing resistor connected between said node and said point of reference potential; and

a third compensating transistor having a similar geometry to that of said second sensing transistor and having its main conduction path connected in parallel with said reference resistor.