Wideband adaptive array using the chirp transform

• US 4,821,037 A
• Filed: 09/10/1986
• Issued: 04/11/1989
• Est. Priority Date: 09/10/1986
• Status: Expired due to Fees

• Current Assignee: Hughes Aircraft Company (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Kerwin, Robert D., Miller, Thomas W.
• Primary Examiner(s): Tarcza, Thomas H.
• Assistant Examiner(s): Hellner, Mark
• Application Number:
  US06/905,824
• Time in Patent Office: 944 Days
• Field of Search: 342/378-381, 342/383, 342/384, 342/201, 342/159, 455/278, 455/296, 364/514, 364/516, 364/577
• US Class Current: 342/383
• CPC Class Codes: H01Q 3/2629 Combination of a main antenna unit with an auxiliary antenna unit
• CPC Class Codes: H03H 21/0027 filtering in the frequency domain

Abstract

An adaptive array processor is disclosed for processing the signals from a main antenna and one or more auxiliary antennas to provide suppression of wideband interference. The outputs from the respective antennas are transformed into the frequency domain by synchronized chirp transformers conducted over a transform block length. The transformed auxiliary antenna signal is weighted by time varying, frequency dependent weights which are adaptively determined. The transformed main antenna and weighted auxiliary antenna signals are then combined. The combined signal is then transformed back to the frequency domain by an inverse chirp transformation.

Claims

1. An array processor for processing signals within a predetermined frequency bandwidth and suppressing interference received by an array of antennas including a main antenna and at least one auxiliary antenna, comprising:

means coupled to the main antenna for transforming the main antenna signal from the time domain into the frequency domain by a chirp transformation conducted over a time interval of duration T, wherein respective frequency components of the main antenna signal appear in time sequence;

means coupled to the auxiliary antenna for transforming the auxiliary antenna signal from the time domain into the frequency domain by a chirp transformation conducted over a time interval T in synchronism with said chirp transformation of the main antenna signal, wherein respective frequency components of the auxiliary antenna signal appear in time sequence;

means for weighting the transformed auxiliary antenna signal by a time variable coefficient in synchronism with said chirp transformation;

means for combining said transformed main antenna signal and said weighted, transformed auxiliary antenna signal to provide a combined transformed array signal; and

means for transforming the combined array signal to the time domain by an inverse chirp transformation to provide an array processor output.

2. The array processor of claim 1 wherein said weighting means provides an adaptively determined coefficient.

3. The array processor of claim 1 wherein said weighting means is adapted to provide a plurality of coefficients, each corresponding to a particular frequency sub-band comprising said frequency bandwidth, and to weight said transformed auxiliary antenna signal by the particular one of the coefficients corresponding to the sub-band of the particular frequency component of said transformed auxiliary antenna signal.

4. The array processor of claim 3 wherein said weighting means further comprises:

means for storing said plurality of coefficients; and

means for recalling said respective coefficients at the appropriate time interval corresponding to the respective frequency sub-band.

5. The array processor of claim 3 wherein said weighting means further comprises variable attenuator means for attenuating said transformed auxiliary antenna signal in dependence on the particular value of said coefficient to provide said weighted, transformed auxiliary antenna signal.

19. An array processor of claim 1 further comprising:

means for coupling said combined transformed array signal from said means for combining to said means for weighting for providing a feedback signal to said means for weighting.

20. An array processor of claim 2 further comprising:

means for coupling said combined transformed array signal from said means for combining to said means for weighting for providing a feedback signal to said means for weighting.

21. An array processor of claim 4 further comprising:

means for coupling said combined transformed array signal from said means for combining to said means for weighting for providing a feedback signal to said means for weighting.

22. An array processor of claim 5 further comprising:

means for coupling said combined transformed array signal from said means for combining to said means for weighting for providing a feedback signal to said means for weighting.

23. An array processor of claim 1 wherein said means for transforming the main antenna signal from the time domain into the frequency domain by a chirp transformation conducted over a time interval of duration T and said means for transforming the auxiliary antenna signal from the time domain into the frequency domain by a chirp transformation conducted over a time interval of duration T each includes:

a first analog chirp transform device for transforming a time domain input signal to a frequency domain output signal in successive first chirp block intervals of duration T;

a second analog chirp transformation device for transforming a time domain input signal to a frequency domain output signal in successive second chirp block intervals of duration T, said first chirp block intervals and said second chirp block intervals being offset in time by a fraction of the block duration T; and

switching means coupled to receive the output signals from said first analog transform device and said second chirp transform device, said switching means alternately switching between the frequency domain output signal from the first chirp transform device and the frequency domain output signal from the second chirp transform device.

24. An array processor of claim 23 further including:

first means for windowing the time domain signal from the main antenna to said first analog chirp transform device and said second chirp transform device of said means for transforming the main antenna signal from the time domain into the frequency domain by a chirp transformation; and

second means for windowing the time domain signal from the auxiliary antenna to said first analog chirp transform device and said second chirp transform device of said means for transforming the auxiliary antenna signal from the time domain into the frequency domain by a chirp transformation.

25. An array processor of claim 24 wherein each said means for windowing provides a Tukey window to said first and second analog chirp transform devices.

26. An array processor of claim 19 wherein said means for transforming the main antenna signal from the time domain into the frequency domain by a chirp transformation conducted over a time interval of duration T and said means for transforming the auxiliary antenna signal from the time domain into the frequency domain by a chirp transformation conducted over a time interval of duration T each includes:

a first analog chirp transform device for transforming a time domain input signal to a frequency domain output signal in successive first chirp block intervals of duration T;

a second analog chirp transformation device for transforming a time domain input signal to a frequency domain output signal in successive second chirp block intervals of duration T, said first chirp block intervals and said second chirp block intervals being offset in time by a fraction of the block duration T; and

switching means coupled to receive the output signals from said first analog transform device and said second chirp transform device, said switching means alternately switching between the frequency domain output signal from the first chirp transform device and the frequency domain output signal from the second chirp transform device.

27. An array processor of claim 26 further including:

first means for windowing the time domain signal from the main antenna to said first analog chirp transform device and said second chirp transform device of said means for transforming the main antenna signal from the time domain into the frequency domain by a chirp transformation; and

second means for windowing the time domain signal from the auxiliary antenna to said first analog chirp transform device and said second chirp transform device of said means for transforming the auxiliary antenna signal from the time domain into the frequency domain by a chirp transformation.

28. An array processor of claim 27 wherein each said means for windowing provides a Tukey window to said first and second analog chirp transform devices.

6. An adaptive array processor for an array comprising a main antenna and at least one auxiliary antenna for receiving signals within a predetermined frequency bandwidth and suppressing interference therein, comprising:

a first chirp transformer means coupled to said main antenna for transforming main antenna signals from the time domain into the frequency domain by the chirp transformation performed over a succession of chirp transform block time-domain intervals;

a second chirp transformer means coupled to said auxiliary antenna for transforming auxiliary antenna signals from the time domain into the frequency domain by the chirp transformation performed over said succession of chirp transform block time-domain intervals;

an auxiliary processor means for providing a sub-band coefficient corresponding to each one of a plurality of predetermined frequency sub-bands comprising said bandwidth, said auxiliary processor means coupled to receive said transformed signals for said second chirp transform means, said auxiliary processor having means for sequentially weighting the output signal from said second chirp transformer means in accordance with said coefficients in synchronism with said chirp transformation to provide an auxiliary processor output signal which is optimized in each frequency subband;

means for combining the transformed main antenna signal and the auxiliary processor output signal to provide a combiner output signal; and

inverse chirp transformer means for transforming the combiner output signal from the frequency domain to the time domain to provide a processor output.

7. The processor of claim 6 wherein said auxiliary processor comprises means for adaptively determining said coefficients.

8. The processor of claim 6 wherein said auxiliary processor comprises:

means for multiplying the combiner output by the output from the second chirp transformer to provide an auxiliary processor error signal;

integrator means coupled to said multiplying means for integrating said error signal over time-domain sub-intervals in said chirp transform block length corresponding to said respective frequency sub-bands;

analog-to-digital converter means coupled to said integrating means for converting said integrated signal into a digital integration value corresponding to the respective frequency sub-band;

coefficient calculation means for adaptively determining a digital coefficient value corresponding to the respective frequency sub-band in dependence on said digital integration value;

digital-to-analog converter means for converting said digital coefficients into analog coefficient values; and

variable attenuator means responsive to said analog coefficient values for attenuating said second chirp transformer output signal by an attenuation factor dependent on said analog coefficient value to provide said auxiliary processor output.

9. The processor of claim 8 wherein said coefficient calculation means comprises:

a digital memory for storing digital coefficient values corresponding to said respective frequency sub-band for the preceding chirp transfer block time-domain interval;

digital adder means coupled to said A/D converter means and said memory means for adding to said digital coefficient value corresponding to said frequency sub-band for the preceding chirp transformer block time-domain interval a digital value proportional to said digital integration value to provide said adaptively determined coefficient value; and

means for storing said adaptively determined coefficient value in said memory.

10. The processor of claim 6 wherein said coefficient is complex-valued, and said adaptive processor comprises means for providing respective in-phase and quadrature components of said complex-valued coefficient.

11. The processor of claim 6 wherein said main antenna comprises a relatively high gain antenna pointed in the angular direction of said signal, said auxiliary antenna comprises a relatively broad-beam antenna, and said array and array processor comprise a sidelobe canceller for cancelling interference sources impinging on the sidelobes of said main antenna.

12. The processor of claim 6 further comprising means for windowing the time domain and auxiliary antenna signals prior to transformation by the chirp transformation to improve interference cancellation.

13. The processor of claim 12 wherein said windowing means is adapted to window said time domain signals by a 50% Tukey window.

14. The processor of claim 6 further comprising means for minimizing edge effects caused by processing finite length block time-domain intervals.

15. The processor of claim 6 wherein said first and second chirp transformer means each comprise:

a first chirp transform device for transforming respective time domain signals in successive first chirp block intervals of finite duration into the frequency domain, wherein respective frequency components of the time domain signal appear in time sequence over the block time-domain interval;

second chirp transform device for transforming respective time domain signals in successive second chirp block intervals of finite duration into the frequency domain, wherein respective frequency components of the time domain signal appear in time sequence over the block time-domain interval, said first and second chirp block intervals being equal in duration but offset in time by a predetermined fraction of the block length; and

multiplexing means coupled to the outputs of said first and second devices to switch between said respective device outputs such that the chirp transformer means output over a particular chirp block time-domain interval comprises said first device output over the middle portion of said first chirp interval and said second device output over the middle portion of said chirp block interval to minimize edge effects caused by processing finite length block time-domain intervals.

16. A method for processing signals in a predetermined frequency bandwidth received by an array of antennas, including a main antenna and at least one auxiliary antenna, comprising a sequence of the following steps:

transforming the main antenna signal from the time domain into the frequency domain by a chirp transformation conducted over a time interval of duration T, wherein respective frequency components of the main antenna signal appear in time sequence;

transforming the auxiliary antenna signal from the time domain into the frequency domain by a chirp transformation conducted over a time interval of duration T in synchronism with the chirp transformation of the main antenna signal, wherein respective frequency components of the auxiliary antenna signal appear in time sequence;

weighting the transformed auxiliary antenna signal by a time variable coefficient in synchronism with said chirp transformation;

subtracting from said transformed main antenna signal said weighted, transformed auxiliary antenna signal; and

transforming the resultant signals back to the time domain by an inverse chirp transformation to provide a processor output signal.

17. The method of claim 16 further comprising the steps of windowing the time domain main and auxiliary antenna signals prior to transformation into the frequency domain to improve interference cancellation performance.

18. The method of claim 16 wherein said respective steps of transforming the main and auxiliary antenna signals each comprises the steps of:

(a) transforming said respective antenna signals over first and second chirp block intervals of equal duration of T seconds, but offset in time by T/2 seconds to provide two sets of transformed signals; and

(b) multiplexing between the two sets of transformed signals to provide a transformer output comprising the portion of the first set of signals appearing over the middle half of the first chirp block interval and the portion of the second set of signals appearing over the middle half of the second chirp block.

29. A method of claim 16 further including the step combining the frequency domain signals resulting from said step of subtracting with the transformed auxiliary antenna signals prior to the step of weighting the transformed auxiliary antenna signals.

30. A method of claim 29 wherein said respective steps of transforming the main and auxiliary antenna signals comprises the steps of:

transforming said main antenna signals over first and second chirp block intervals of equal duration T, said first and second block intervals being offset in time by a fraction of the block interval T to provide overlapping transformed signals from the main antenna;

transforming said auxiliary antenna signals over first and second chirp block intervals of equal duration T, said first and second block intervals being offset in time by a fraction of the block interval T to provide overlapping transformed signals from the auxiliary antenna;

alternately selecting a portion of the transformed main antenna signal from the first block interval and a portion of the main antenna signal from the second block interval to provide the transformed main antenna signal; and

alternately selecting a portion of the transformed auxiliary antenna signal from the first block interval and a portion of the auxiliary antenna signal from the second block interval to provide the transformed auxiliary antenna signal.

31. A method of claim 30 further comprising the steps of windowing the time domain main and auxiliary antenna signals prior to transformation into the frequency domain.

32. A method of claim 31 wherein said first and second block intervals are offset by approximately one half of the block interval T.

33. A method of claim 32 wherein said steps of alternately selecting a portion of the transformed main and auxiliary antenna signals comprises alternately selecting a portion over the middle portion of said block intervals.

34. A method of claim 31 wherein said steps of alternately selecting a portion of the transformed main and auxiliary antenna signals comprises alternately selecting a portion over the middle portion of said block intervals.