Internal performance monitoring by event sampling
First Claim
1. Internal processor instrumentation means for monitoring the software/hardware operations of a data processing system, which includes one or more processors, a system control console having displaying screens under control of a system operator;
- each processor having machine cycling circuits, and I/O controls;
each processor having a plurality of internal lines for transferring internal signals including signals indicating processor condition states;
an event-driven monitoring means comprising;
signal collection means for registering internal signals occurring during one or more machine cycles, the signal collection means being connected to and located in proximity to internal signal lines in a processor,condition selection logic means having inputs connected to internal lines for receiving selected internal signals indicating condition states in the processor and determining the condition states to be used in the determination of monitoring events in event-driven monitoring operations for the processor,event selection logic means having inputs connected to the signal collection means and to the condition selection logic means, the event selection logic means determining the occurrence of a monitoring event from selected inputs from the condition selection logic means and the event selection logic means, and the event selection logic means having an output for signalling the occurrence of a monitoring event to be used in a monitoring operation,an internal instrumentation table unit (ITU) having an instrumentation table array (ITA) that includes a plurality of ITA entries and includes addressing means for selecting a current entry in the ITA,gating means being associated with the signal collection means for selecting and transmitting registered internal signals from the collection means to the ITU, the gating means being enabled by the occurrence of the monitoring event determined by the event selection logic means, the gating means transmitting selected signals from the collector means to the current entry in the ITA when a monitoring event is determined to have occurred by the event selection logic means, and the ITU temporarily storing the internal signals transmitted by the gating means to the ITA, andrecording means being connected to the ITU for receiving the event monitored data temporarily stored in the ITA entries when the ITA is filled during an event-driven monitoring operation for the processor.
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Abstract
The disclosure provides event-controlled operations for an internal hardware/softward monitor for a processor in a data processing system. It embeds and distributes in each processor at least one instrumentation table unit (ITU) and event detection circuitry to detect events and conditions for collecting event-sampled hardware signals provided in the processor hardware in which the respective ITU is embedded. Instrumentation measurement is controlled centrally in the system. Sampling of the CPU signals for recording in the ITU is done at (or a sub-multiple of) the occurrence rate of the selected event(s) in the processor. The sampled signals are recorded in the ITU. The ITUs of plural processors are asynchronously operated in a system. The event-driven monitoring circuitry may be solely provided in an ITU, or it may be superimposed on a timer-driven internal instrumentation system of the type described in U.S. Pat. No. 4,590,550 in which the ITU is shared between event and timer driven modes of operation. Branch-taken event monitoring is also included in the disclosure.
274 Citations
14 Claims
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1. Internal processor instrumentation means for monitoring the software/hardware operations of a data processing system, which includes one or more processors, a system control console having displaying screens under control of a system operator;
- each processor having machine cycling circuits, and I/O controls;
each processor having a plurality of internal lines for transferring internal signals including signals indicating processor condition states;
an event-driven monitoring means comprising;signal collection means for registering internal signals occurring during one or more machine cycles, the signal collection means being connected to and located in proximity to internal signal lines in a processor, condition selection logic means having inputs connected to internal lines for receiving selected internal signals indicating condition states in the processor and determining the condition states to be used in the determination of monitoring events in event-driven monitoring operations for the processor, event selection logic means having inputs connected to the signal collection means and to the condition selection logic means, the event selection logic means determining the occurrence of a monitoring event from selected inputs from the condition selection logic means and the event selection logic means, and the event selection logic means having an output for signalling the occurrence of a monitoring event to be used in a monitoring operation, an internal instrumentation table unit (ITU) having an instrumentation table array (ITA) that includes a plurality of ITA entries and includes addressing means for selecting a current entry in the ITA, gating means being associated with the signal collection means for selecting and transmitting registered internal signals from the collection means to the ITU, the gating means being enabled by the occurrence of the monitoring event determined by the event selection logic means, the gating means transmitting selected signals from the collector means to the current entry in the ITA when a monitoring event is determined to have occurred by the event selection logic means, and the ITU temporarily storing the internal signals transmitted by the gating means to the ITA, and recording means being connected to the ITU for receiving the event monitored data temporarily stored in the ITA entries when the ITA is filled during an event-driven monitoring operation for the processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
- each processor having machine cycling circuits, and I/O controls;
Specification