Display processors accommodating the description of color pixels in variable-length codes

• US 4,821,208 A
• Filed: 10/14/1986
• Issued: 04/11/1989
• Est. Priority Date: 06/18/1986
• Status: Expired due to Term

• Current Assignee: Intel Corporation, RCA Corporation
• Original Assignee: Technology, Inc.
• Inventors: Caracciolo, Gerald T., Shedd, Robert D., Sherrill, James V., Ryan, Lawrence D.
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): HERNDON, HEATHER R
• Application Number:
  US06/918,305
• Time in Patent Office: 910 Days
• Field of Search: 364/518-521, 340/701-703, 340/721, 340/723, 340/747, 340/798-800
• US Class Current: 345/550
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables

Abstract

A display processor, as for a small computer, processes pixel codes of various lengths. Three addressable color maps have their read addresses generated independently from portions of each pixel code. The portions of each pixel code used in generating each read address can be selected by programming.

Claims

1. A display processor for conditioning pixel data for use by a utilization means such as a kinescope, said processor comprising:

a first color map memory addressable by a first read address of p bits during its reading, p being a positive integer;

a first pre-address register for temporarily storing a p-bit first pre-address;

means for generating from said p-bit first pre-address said first read address;

a second color map memory addressable by a second read address of q bits during its reading, q being a positive integer;

a second pre-address register for temporarily storing a q-bit second address;

means for generating from said q-bit second pre-address said second read address;

a pixel input latch having a minimum width of (p+q) bits into which the data for respective pixels are serially loaded;

means for selecting from the contents of said pixel input latch a first number of bits from adjacent bit places, said first number being no larger than p;

means for applying the first number of bits in justified format to said first pre-address register as at least a portion of said first pre-address and applying ZEROs as any remaining portion of said first pre-address, to be temporarily stored in said first pre-address register;

means for programmably selecting from the contents of said pixel input latch second number of bits from adjacent bit places, said second number being no larger than q;

said means for programmably selecting a second number of bits being of a type in which there is a choice of which bit places are to be included in said second number that is independent of which bit places are included in said first number;

means for applying the second number of bits in justified format to said second pre-address register as at least portion of said second pre-address and applying ZEROs as any remaining portion of said second pre-address, to be temporarily stored in said second pre-address register; and

means coupled to said first and second color maps memories for applying data read from said color map memories to said utilization means.

2. A display processor as set forth in claim 1 having a minimum width of (p+q+r) bits in its said input latch and further including:

a third color map memory addressable by a third read address of r bits during its reading, r being a positive integer;

a third pre-address register for temporarily storing an r-bit third pre-address;

means for generating from said r-bit third pre-address said third read address;

means for programmably selecting from the contents of said pixel input latch a third number of bits from adjacent bit places, said third number being no larger than r, said means for programmably selecting a third number of bits being of a type in which there is a choice of which bit places are to be included in said third number that is independent of which bit places are included in said first number and in said second number respectively;

means for applying the third number of bits in justified format to said third pre-address register as at least a portion of said third pre-address and applying ZEROs as any remaining portion of said third pre-address, to be temporarily stored in said third pre-address register; and

means for coupling said third color map memory to said utilization means.

3. A plurality of display processors as set forth in claim 2 in combination with;

means for providing time division multiplexed operation of said plurality of display processors.

4. A pair of display processors as set forth in claim 1 in combination with;

means for providing parallel operation of said pair of display processors.

5. A display processor as set forth in claim 1 wherein said justified format is one in which justification is in the direction of increased significance.

6. A display processor as set forth in claim 1 wherein said justified format is one which justification is in the direction of decreased significance.

7. A display processor as set forth in claim 1 wherein said means for selecting from the contents of said pixel input latch a first number of bits is of a type that selects the most significant bits in said pixel input latch.

8. A display processor as set forth in claim 1 wherein said means for selecting from the contents of said pixel input latch a first number of bits is of a type that selects the least significant bits in said pixel input latch.

9. A display processor as set forth in claim 1 further including:

a third color map memory addressable by said first read address.

10. A display processor for conditioning pixel data for use by a utilization means such as a kinescope, said processor comprising:

a first color map memory addressable by a first read address of p bits during its reading, p being a positive integer;

a first pre-address register for temporarily storing a p-bit first pre-address;

a first index register storing a first index therein;

means for combining said first index with said first pre-address temporarily stored in said first pre-address register to generate said first read address;

a second color map memory addressable by a second read address of q bits during its reading, q being a positive integer;

a second pre-address register for temporarily storing a q-bit second pre-address;

means for generating from said q-bit second pre-address said second read address;

a pixel input latch having a minimum width of (p+q) bits into which the data for respective pixels are serially loaded;

means for selecting from the contents of said pixel input latch a first number of bits, said first number being no larger than p;

means for applying the first number of bits in justified format to said first pre-address register as at least a portion of said first pre-address and applying ZEROs as any remaining portion of said first pre-address, to be temporarily stored in said first pre-address register;

means for selecting from the contents of said pixel input latch a second number of bits, said second number being no larger than q;

said means for selecting a second number of bits being of a type in which there is a choice of which bit places are to be included in said second number that is independent of which bit places are included in said first number;

means for applying the second number of bits in justified format to said second pre-address register as at least a portion of said second pre-address and applying ZEROs as any remaining portion of said second pre-address, to be temporarily stored in said second pre-address register; and

means coupled to said first and second color map memories for applying data read from said color map memories to said utilization means.

11. A display processor as set forth in claim 10 wherein said utilization means includes:

digital-to-analog converter means for converting to respective analog signals the streams of successive digitized read-outs from said first, second and third color map memories; and

color matrixing circuitry for converting those analog signals to analog signals each descriptive of a respective additive primary color component.

12. A combination as set forth in claim 11 further including means for providing spatial interpolation to the read-out from at least one of said first, second and third color map memories prior to its conversion to a respective analog signal by said digital-to-analog converter means.

13. A combination as set forth in claim 11 further including:

a color kinescope; and

first, second and third video amplifiers for supplying to said color kinescope as blue, red and green drive signals amplified responses to the continuous analog signals supplied to said video amplifiers from said analog-to-digital converter means.

14. A display processor as set forth in claim 10 wherein said means for combining said first index with the first pre-address consists of:

a first rank of OR gates ORing the bits temporarily stored in said first pre-address register with respective bits of said first index register to generate said first read address.

15. A display processor as set forth in claim 10;

wherein said means for generating said second read address includes;

a second index register storing a second index therein; and

means for combining said second index with the second pre-address temporarily stored in said second pre-address register to generate said second read addresses.

16. A display processor as set forth in claim 15 wherein said means for combining said second index with the second pre-address consists of:

a second rank of OR gates ORing the bits temporarily stored in said second pre-address register with respective bits of said second index register to generate said second read address.

17. A display processor for conditioning pixel data for use by a utilization means such as a kinescope, said processor comprising:

a pixel input latch having a minimum width of (p+q+r) bits into which the data for respective pixels are serially loaded, p, q and r being positive integers;

a first color map memory addressable by a first read address of p bits;

a first pre-address register for temporarily storing a p-bit first pre-address;

means for selecting from the contents of said pixel input latch a first number of bits, said first number being no larger than p;

means for applying the first number of bits in justified format to said first pre-address register as at least a portion of said pre-address and applying ZEROs as any remaining portion of said first pre-address;

to be temporarily stored in said first pre-address register;

a first index register storing a first index therein having a number of bits therein corresponding to the number of bits in any remaining portion of said first pre-address;

means for combining said first index with said first pre-address temporarily stored in said first pre-address register to generate said first read address;

a second color map memory addressable by a second read address of q bits;

a second pre-address register for temporarily storing a q-bit second address;

means for selecting from the contents of said pixel input latch a second number of bits, said second number being no larger than q;

said means for selecting a second number of bits being a type in which there is a choice of which bit places are to be included in said second number that is independent of which bit places are included in said first number;

means for applying the second number of bits in justified format to said second pre-address register as at least a portion of said second pre-address and applying ZEROs as any remaining portion of said second pre-address, to be temporarily stored in said second pre-address register;

means for generating from said q-bit second pre-address said second read address;

a third color map memory addressable by a third read address of r bits;

a third pre-address register for temporarily storing an r-bit third pre-address;

means for selecting from the contents of said pixel input latch a third number of bits, said third number being no larger than r, said means for selecting a third number of bits being of a type in which bit places are selected independent of which bit places are included in said first and second numbers of bits

means for applying the third number of bits in justified format to said third pre-address register as at least a portion of said third pre-address and applying zeros as any remaining portion of said third pre-address, to be stored in said third pre-address register;

means for generating from said r-bit third pre-address said third read address; and

means for coupling data read from said first, second and third color map memories to said utilization means.

18. A display processor as set forth in claim 17 wherein said utilization means comprises:

a color kinescope;

digital-to-analog convertor means for converting the streams of successive digitized read-outs from said first, second and third color map memories, to respective continuous analog signals each descriptive of a respective additive primary color component; and

first, second and third video amplifiers for supplying to said color kinescope as blue, red and green drive signals amplified responses of the continuous analog signals supplied to said video amplifiers from said digital-to-analog converter means.

19. A display processor as set forth in claim 17 wherein said means for combining said first index with the first pre-address consists of:

a first rank of OR gates ORing the bits of said any remaining portion of said first pre-address with bits of said first index to generate said first read address.

20. A display processor as set forth in claim 17, wherein said means for generating said second read address includes:

a second index register storing a second index therein having a number of bits therein corresponding to the number of bits in any remaining portion of said second pre-address; and

means for combining said second index with the second pre-address temporarily stored in said second pre-address register to generate said second read addresses.

21. A display processor as set forth in claim 20 wherein said means for combining said second index with the second pre-address consists of:

a second rank of OR gates ORing the bits of said any remaining portion of said second pre-address with bits of said second index to generate said second read address.

22. A display processor as set forth in claim 20, wherein said means for generating said third read address includes:

a third index register storing a third index therein having a number of bits therein corresponding to the number of bits in any remaining portion of said third pre-address; and

means for combining said third index with the third pre-address temporarily stored in said third pre-address register to generate said third read address.

23. A display processor as set forth in claim 22 wherein said means for combining said third index with the third pre-address consists of:

a third rank of OR gates ORing the bits of said any remaining portion of said third pre-address with bits of said third index to generate said third read address.

24. A display processor for conditioning pixel data for use by utilization means such as a kinescope, said processor comprising:

a first color map addressable by a first read address of p bits, p being a positive integer;

a first pre-address register for temporarily storing a p-bit first pre-address;

a first index register storing a first index therein;

means for combining said first index with first pre-address temporarily stored in said first pre-address register to generate said first read address;

a second color map memory addressable by a second read address of q bits, q being a positive integer;

a second pre-address register for temporarily storing a q-bit second address;

means for generating from said q-bit second pre-address said second read address;

a third color map memory addressable by said first read address;

a pixel input latch having a minimum width of (p+q) bits into which the data for respective pixels are serially loaded;

means for selecting from the contents of said pixel input latch a first number of bits, said first number being no larger than p;

means for supplying the first number of bits in justified format to said first pre-address register as at least a portion of said first pre-address and applying ZEROs as any remaining portion of said first pre-address, to be temporarily stored in said first pre-address register;

means for selecting from the contents of said pixel input latch a second number of bits, said second number being no larger than q;

said means for selecting a second number of bits being of a type in which there is a choice of which bit places are to be included in said second number that is independent of which bit places are included in said first number;

means for applying the second number of bits in justified format to said second pre-address register as at least a portion of said second pre-address and applying ZEROs as any remaining portion of said second pre-address to be temporarily stored in said second pre-address register; and

means for coupling data read from said first, second and third color map memories to said utilization means.

25. A display processor as set forth in claim 24 wherein said means for selecting from the contents of said pixel input latch a first number of bits is of a type that selects the most significant bits in said pixel input latch.

26. A display processor as set forth in claim 24 wherein said means for selecting from the contents of said pixel input latch a first number of bits is of a type that selects the least significant bits in said pixel input latch.

27. A display processor as set forth in claim 24 wherein said utilization means includes:

digital-to-analog convertor means for converting to respective analog signals the streams of successive digitized read-outs from said first, second and third color map memories; and

color matrixing circuitry for converting those analog signals to analog signals each descriptive of a respective additive primary color component.

28. A combination as set forth in claim 27 further including means for providing spatial interpolation to the read-out from at least one of said first, second and third color map memories prior to its conversion to a respective analog signal by said digital-to-analog converter means.

29. A combination as set forth in claim 27 further including:

a color kinescope; and

first, second and third video amplifiers for supplying to said color kinescope as blue, red and green drive signals amplified responses to the continuous analog signals supplied to said video amplifiers from said analog-to-digital converter means.

30. A display processor as set forth in claim 24 wherein said means for combining said first index with the first pre-address consists of:

a first rank of OR gates ORing the bits temporarily stored in said first pre-address register with respective bits of said first index register to generate said first read address.

31. A display processor as set forth in claim 30;

wherein said means for generating said second read address includes;

a second index register storing a second index therein; and

means for combining said second index with the second pre-address temporarily stored in said second pre-address register to generate said second read addresses.

32. A display processor as set forth in claim 31 wherein said means for combining said second index with the second pre-address consists of:

a second rank of OR gates ORing the bits temporarily stored in said second pre-address register with respective bits of said second index register to generate said second read address.

33. A display processor as set forth in claim 24;

wherein said means for generating said second read address includes;

a second index register storing a second index therein; and

means for combining said second index with the second pre-address temporarily stored in said second pre-address register to generate said second read address.

34. A display processor as set forth in claim 33 wherein said means for combining said second index with the second pre-address consists of:

a second rank of OR gates ORing the bits temporarily stored in said second pre-address register with respective bits of said second index register.

35. A display processor as set forth in claim 24 wherein said justified format is one which justification is in the direction of increased significance.

36. A display processor as set forth in claim 24 wherein said justified format is one which justification is in the direction of decreased significance.

37. In combination:

a source of multi-bit pixel data words;

first and second display processors each first, second and third color map memories;

means for storing multi-bit pixel data words;

means for generating read addresses for said first color map memory from a selected portion of the bits in each word of pixel data;

first programmable means for selecting bits of said multi-bit words of pixel data independently of the portion of the bits used in generating said read address for the first color map memory, and generating read addresses for said second color map memory;

second programmable means for selecting bits of said multi-bit words of pixel data independently of the bits used in generating said read addresses for the first and second color map memories, and generating read addresses for

said third color map memory;

means coupled to said source, for apportioning said multi-bit pixel data words to the means for storing multi-bit pixel data words of said first and second display processors; and

means responsive to data read out from each of said first, second and third color map memories of said first and second display processors for generating a color display image.

38. A display processor for conditioning pixel data for display, said pixel data occurring as multi-bit codewords and capable of being coded in different formats, said processor comprising:

an input port for receiving said pixel data;

storage means coupled to said input port for storing codewords of said pixel data and for providing respective bits of said multi-bit codewords;

first and second color map memories having respective address input ports and respective data output ports;

first means for selecting one of bits of said multibit codeword provided by said storage means in accordance with a particular format in which said pixel data is provided;

means for coupling said selected ones of bits in justified form to the address input port of said first color map memory;

second means for programmably selecting bits of said multibit codewords provided by said storage means independently of said ones of bits selected by said first means and in accordance with said format in which said pixel data is provided;

means for couplinng bits of said multibit codewords selected by said second means, in justified form, to the address input port of said second color map memory; and

utilization means coupled to the data output ports of said color map memories.