Planar display device

• US 4,822,142 A
• Filed: 12/23/1986
• Issued: 04/18/1989
• Est. Priority Date: 12/23/1986
• Status: Expired due to Term

• Current Assignee: TPO Hong Kong Holding Limited (InnoLux Corporation)
• Original Assignee: Hosiden Electronics Co. Ltd. (Hosiden Corporation)
• Inventors: Yasui, Masaru
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Duong, Tai V.
• Application Number:
  US06/945,701
• Time in Patent Office: 847 Days
• Field of Search: 350/332, 350/333, 350/334, 350/339 F, 340/784, 340/702, 340/765
• US Class Current: 349/48
• CPC Class Codes: G09G 2300/0452 Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2003 Display of colours specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 3/3607 for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

A planar display device is disclosed, which comprises a plurality of display elements in rows and columns, row drive lines each commonly connected to two adjacent rows of display elements and column drive lines are provided in pairs each for each column of display elements, every other one of the display elements in a column being connected to one of the pair of column drive lines, and the other display elements in the column being connected to the other column drive lines in the pair. Each of the display elements is selectively activated by the row and column drive lines connected thereto.

Claims

1. A planar display device comprising:

a plurality of display elements respectively defined by display electrodes arrayed in rows and columns to form a matrix array of said display elements;

a plurality of first thin film transistors each having a drain source, drain and gate formed adjacent a corresponding one of said display electrodes, each of said first transistors having its drain connected to a corresponding one of said display electrodes;

a plurality of first row drive lines each provided for and extending between every two adjacent rows of said display electrodes, said first transistors connected to corresponding ones of said display electrodes on the opposite sides of each said first row drive line having their respective gates commonly connected to said first row drive line;

a plurality of column drive lines provided in pairs for respective columns of said display electrodes, said column drive lines in each pair extending along opposite sides of a corresponding column of said display electrodes, said first transistors connected to respective said display electrodes in said corresponding column having their respective sources connected alternately to one and the other of said pair of column drive lines;

a plurality of second row drive lines each provided for and extending between every two adjacent rows of said display electrodes between adjacent ones of said first row drive lines;

a plurality of second thin film transistors each having a source, drain and gate formed adjacent corresponding ones of said display electrodes each of said second transistors having its drain connected to a corresponding one of said display electrodes, said second transistors connected to said corresponding ones of said display electrodes on the opposite sides of each said second row drive line having their respective gates commonly connected to said second row drive line, and each of said second transistors having its source connected to one of a corresponding pair of said column drive lines other than the one to which the source of a corresponding one of said first transistors is connected;

row drive means connected to said first and second row drive lines for driving said plurality of first row drive lines one after another in synchronism with the horizontal scanning cycle of a video signal for each odd scanning field, and for driving said plurality of second row drive lines one after another in synchronism with the horizontal scanning cycle of the video signal for each even scanning field; and

column drive means supplied with said video signal for each scanning line and having a plurality of drive stages equal in number to said plurality of column drive lines and connected thereto, respectively, for driving said column drive lines according to the outputs of corresponding said stages.

2. The planar display device according to claim 1 wherein red, green and blue color filters are provided on respective said display elements to form three-color display element sets such that said color filters are substantially uniformly distributed as a whole, two of the three color display elements in each set in a column and the other color display element in an adjacent column constituting one picture point with respect to a first row drive line.

3. The planar display device according to claim 2 wherein said video signal consists of serial pixel signals each consisting of parallel red, green and blue color element signals, and said device further comprises a shift register supplied with a horizontal sync pulse as data which is shifted in said register under control of a clock signal at three times the frequency of the color pixel signals, first to third color signal buses through which the three color element signals are successively and repeatedly supplied to corresponding stages of said column drive means according to the data shifted through said shift register, and means for switching the connection between input lines, to which said red, green and blue color element signals are supplied, and said first two third color signal buses, in synchronism with said horizontal sync pulse.

4. The planar display device according to claim 1 wherein red, green and blue color filters are provided on respective said display elements to form three-color display element sets such that said color filters are substantially uniformly distributed as a whole, two of the three color display elements in each set in a column and the other color display element in an adjacent column constituting one picture point with respect to a first row drive line.

5. The planar display device according to claim 2 or 4 comprising:

first to third color signal buses, to which red, green and blue color element signals constituting each of a series of pixel signals are supplied in parallel;

delay means connected to said first to third color signal buses for delaying each of the red, green and blue color element signals for one cycle period of said pixel signals;

fourth to sixth color signal buses connected to the output side of said delay means for delivering said red, green and blue color element signals each delayed for one cycle period of said pixel signals;

a shift register which is supplied with the horizontal sync pulses of said video signal as data, and which is also supplied with a clock signal as a shift clock of one half the frequency of the pixel signals, for producing a plurality of timing signals at respective stages of said shift register; and

a plurality of column registers each supplied with the color element signals on said first to sixth color signal buses in response to the timing signals from the respective stages of said shift register for supplying six outputs of each said column register to corresponding ones of said column drive lines.

6. The planar display device according to one of claims 1, 2, 3 and 4 wherein said planar display device is a liquid crystal display device.