Method of fabricating large area semiconductor arrays
First Claim
1. A method for separating integrated circuit chips formed on a crystalline substrate comprising the steps of(a) forming a plurality of vertical trenches along predetermined intersecting lateral boundaries on the top surface of said substrate by a reactive ion etch process,(b) filling in said trenches with an etchable material,(c) forming a plurality of integrated circuits on the surface of said substrate with said lateral boundaries,(d) passivating both surfaces of said substrate,(e) and etching a plurality of grooves on the back of the wafer in general alignment with said vertical trenches, said etching being adapted to etch into, and free said trenches from said etchable material,whereby said integrated circuits are separated by the combined action of said top and bottom etching steps, said circuits being formed with planar butting surfaces created by the vertical trench formation.
4 Assignments
0 Petitions
Accused Products
Abstract
A method for separating chips formed on a silicon substrate is provided which uses a combination of reactive ion etching techniques combined with orientation etching to yield integrated chips having edges which can be more precisely butted together to form large area arrays.
83 Citations
13 Claims
-
1. A method for separating integrated circuit chips formed on a crystalline substrate comprising the steps of
(a) forming a plurality of vertical trenches along predetermined intersecting lateral boundaries on the top surface of said substrate by a reactive ion etch process, (b) filling in said trenches with an etchable material, (c) forming a plurality of integrated circuits on the surface of said substrate with said lateral boundaries, (d) passivating both surfaces of said substrate, (e) and etching a plurality of grooves on the back of the wafer in general alignment with said vertical trenches, said etching being adapted to etch into, and free said trenches from said etchable material, whereby said integrated circuits are separated by the combined action of said top and bottom etching steps, said circuits being formed with planar butting surfaces created by the vertical trench formation.
Specification