Vertical MOSFET having Schottky diode for latch-up prevention
First Claim
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1. A vertical MOS filed effect semiconductor device comprising:
- a substrate comprising a first semiconductor layer of a first conductivity type, said substrate having a first surface formed by said first semiconductor layer, and a second surface,a drain electrode formed on said second surface of said substrate,a channel region of a second conductivity type opposite to said first conductivity type, formed in said first semiconductor layer,a source region of said first conductivity type, surrounded by said semiconductor channel region,a gate electrode formed above said channel region between said source region and said first semiconductor layer, and separated from said channel region by a gate insulating layer, anda metal source electrode having a first portion extending into said substrate from said first surface, passing through said source region and said channel region and terminating at an innermost end which forms a first Schottky junction with said first semiconductor layer at a location remote from said first surface.
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Abstract
In a vertical MOSFET of a conductivity modulated type or a standard type, including an n epitaxial layer grown on a p+ or n+ substrate, a p type channel region, and an n+ source region, there is further provided a Schottky diode which is formed between the n epitaxial layer and a metal source electrode extending through the source region and channel region and reaching the epitaxial layer under the source and channel regions in order to prevent latch-up of a parasitic thyristor.
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Citations
15 Claims
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1. A vertical MOS filed effect semiconductor device comprising:
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a substrate comprising a first semiconductor layer of a first conductivity type, said substrate having a first surface formed by said first semiconductor layer, and a second surface, a drain electrode formed on said second surface of said substrate, a channel region of a second conductivity type opposite to said first conductivity type, formed in said first semiconductor layer, a source region of said first conductivity type, surrounded by said semiconductor channel region, a gate electrode formed above said channel region between said source region and said first semiconductor layer, and separated from said channel region by a gate insulating layer, and a metal source electrode having a first portion extending into said substrate from said first surface, passing through said source region and said channel region and terminating at an innermost end which forms a first Schottky junction with said first semiconductor layer at a location remote from said first surface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification