Electrically alterable, nonvolatile floating gate memory device

• US 4,823,175 A
• Filed: 05/27/1987
• Issued: 04/18/1989
• Est. Priority Date: 06/03/1986
• Status: Expired due to Term

• Current Assignee: SGS Microelettronica SpA (STMicroelectronics NV)
• Original Assignee: SGS Microelettronica SpA (STMicroelectronics NV)
• Inventors: Fontana, Gabriella
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): PRENTY, MARK V
• Application Number:
  US07/054,712
• Time in Patent Office: 692 Days
• Field of Search: 357/23.5, 357/54, 365/185
• US Class Current: 257/321
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Disclosed is an electrically alterable, floating gate type, nonvolatile, semiconductor memory device wherein the gate oxide layer in the "injection" area between the silicon (drain region of the device) and the floating gate has an increased thickness with respect to the thickness of the same gate oxide layer over the channel region of the device in order to decrease the parasitic capacitance of the injection area, thus improving the programming threshold voltage characteristics. A method for fabricating the improved memory device is also disclosed.

Claims

1. An electrically alterable, floating gate type, nonvolatile, semiconductor memory device comprising:

a substrate of a semiconductor material having a channel region of a first type of conductivity contained between a first and a second region of a second type of conductivity, formed at the surface of said substrate of semiconductor material, said channel region providing a region in the semiconductor material capable of passing an electric current between said first and said second region;

a first level of conducting material forming a floating gate extending over said channel region between said first and said second region and over an injection area above one of said first and a second region, said floating gate being electrically insulated from the semiconductor material by a layer of gate oxide having an injection window within said injection area, the insulating layer within said window being represented by a layer of tunnel oxide essentially thinner than the layer of gate oxide; and

a second level of conducting material, insulated from said first level of conducting material and forming a control gate of the device;

a select MOS transistor being associated with said memory device, substantially in electrical series thereof;

wherein, the reference to said injection area, that portion of said insulating layer of gate oxide between said floating gate and the relevant one of said first or second region, except for the area of said injection window, has a thickness greater than the thickness of the portion of said layer of gate oxide superposing over said channel region, and said select MOS transistor has a gate oxide having the same thickness as the gate oxide present over said injection area of the memory device.