Vertical double diffused metal oxide semiconductor (VDMOS) device including high voltage junction exhibiting increased safe operating area
First Claim
1. A semiconductor field effect device comprising:
- a body of semiconductor material having a major surface; and
an insulated gate electrode grid disposed on said major surface, said grid comprising;
as plurality of spaced apart first gate segments, each of said first segments being substantially circular, anda plurality of second gate segments, each of said second segments extending between, and interconnecting, two adjacent one s of said first segments.
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Abstract
A power field effect device has a high voltage blocking junction which intersects the device surface under the gate electrode. That intersection is a closed plane geometric figure whose center is within the body region of the device rather than in the more heavily doped base region of the device. The figure preferably is everywhere convex and has a maximum width of substantially less than the depletion width, at breakdown, of a corresponding parallel plane junction. The device breakdown voltage is higher than the breakdown voltage of a corresponding junction having a cylindrical edge with a straight axis. In a preferred embodiment, the high voltage blocking junction has a plurality of such intersections with the device surface, each situated beneath a segment of the gate electrode. In a bipolar embodiment, the gate electrode may be omitted.
159 Citations
32 Claims
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1. A semiconductor field effect device comprising:
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a body of semiconductor material having a major surface; and an insulated gate electrode grid disposed on said major surface, said grid comprising; as plurality of spaced apart first gate segments, each of said first segments being substantially circular, and a plurality of second gate segments, each of said second segments extending between, and interconnecting, two adjacent one s of said first segments. - View Dependent Claims (2, 3, 16, 17, 30)
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4. A semiconductor device comprising a body of semiconductor material having:
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a first major surface; a first region of one type conductivity extending to said first major surface; a second region of opposite type conductivity extending into said first region from said first surface and forming a PN junction with said first region; and an insulated gate electrode grid disposed on said first major surface, said grid comprising; a plurality of spaced apart first gate segments, and a plurality of second gate segments, each of said second gate segments extending between and interconnecting, two of said first gate segments, said second region being more heavily doped than said first region and having a plurality of spaced apart openings therein at which said PN junction and said first region extend to said first surface, each of s°
i openings being substantially aligned with a different said first gate segments, and at each of said openings, the intersection of said PN junction with said first major surface being a closed plane geometric figure having a maximum width of less than 4 DB wherein DB is the break voltage depletion width for a parallel plane PN junction between said first and second regions. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 18, 19, 20, 21, 22, 29)
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23. A semiconductor field effect device comprising a body of semiconductor material having:
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first and second major surfaces; a first region of one type conductivity material extending to said first major surface; a second region of opposite type conductivity more heavily doped than said first surface and forming a first PN junction therewith, said second region having a plurality of openings therein at each of which said first region extends to said first surfaces; a third region of said one type conductivity extending into said second region form said first surface and spaced from said first region by said second region; and an insulated gate electrode having a plurality of spaced part first segments each overlying said first layer wherein it extends to said first surface at a different one of said openings, one of said first gate segments overlying the portion of said second region which spaces said third region from said first layer and a portion of said third region; said insulated gate electrode including a plurality of second segments each of which connects two of said first gate segments; said first PN junction intersecting said first major surface under said gate electrode layer at each of said openings, each of said intersections comprising a closed plane geometric figure whose center is within said first region and whose maximum width is less than 4 DB where DB is the breakdown voltage depletion width of a parallel plane PN junction between said first and second region. - View Dependent Claims (24, 25, 31)
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26. A semiconductor device comprising a body of semiconductor material having:
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a first major surface; a first region of one type conductivity; a second region of opposite type conductivity extending into said first region form said first surface and forming a PN junction with said first region; said second region being more heavily dope than said first region and having a plurality of openings therein at which said PN junction and said first region extend to said first surface, each intersection of said PN junction with said first major surface being a closed plane geometric figure which is everywhere convex; and a plurality of third regions of said one type conductivity extending into said second region from said second surface and spaced from said first region by said second region; an insulated gate electrode grid disposed on said first major surface, said grid comprising; a plurality of spaced apart first gate segments, each of said first gate segments overlying a different one of said plurality of openings, extending across the portion of said second region which is disposed between said first region within said opening and one of said third regions which is disposed adjacent thereto and being spaced from the others of said openings, and a plurality of second gate segments extending between, and interconnecting two of said first gate segments. - View Dependent Claims (27, 28, 32)
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Specification