Reconfigurable dual processor system

• US 4,823,256 A
• Filed: 06/22/1984
• Issued: 04/18/1989
• Est. Priority Date: 06/22/1984
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: American Telephone & Telegraph Company (AT&T, Inc.)
• Inventors: Schmitt, David A., Hansen, Robert C., Butvila, Jonas, Fitch, David J., Surratt, Grover T., Bishop, Thomas P.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Fairbanks, Jonathan C.
• Application Number:
  US06/623,481
• Time in Patent Office: 1,761 Days
• Field of Search: 371/8, 371/9, 371/11, 371/68, 364/200 MS File, 364/900 MS File, 364/187, 364/134, 179/18 EE, 179/18 ES, 379/279, 379/284
• US Class Current: 714/10
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 11/2007 using redundant communication media
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups
• CPC Class Codes: G06F 2201/845 Systems in which the redundancy can be transformed in increased performance

Abstract

A is a duel processor system (100) with duplicated memory (114,124) has two modes (10,11) of operation: a converged mode (10) in which one of the two processors (101,102) is active and executing all system tasks while the other processor is inactive; and a diverged mode (11) in which both processors are active and independently executing different tasks. The system automatically changes modes in response to requests such as manual and program control and certain system fault conditions. In diverged mode, the system may be in either of two states of operation (1 and 2). In one state (1) one processor (101) is designated a primary processor, and in the other state (2) the other processor (102) is designated the primary processor. In the converged mode the system may be in either of four states of operaton (3-6). In two of these states (3,4) one processor is active while the other processor is standing by ready to take up execution of tasks from the point where the one processor stoped execution. In the other two of these states (5,6) one processor is active while the other processor is out of service and cannot take up task execution without being initialized. The system 100 makes transitions between the various states in response to requests. Except for transitions of an active processor to an out-of-service condition, the state transitions are transparent to tasks other than fault recovery programs and, upon a fault condition, the faulted program.

Claims

1. A processing system comprising:

a first and a second processor;

a first main memory included in the first processor and a second main memory included in the second processor, the first and second main memories having the same contents;

means interconnecting the first and the second memories, when active for automatically updating each main memory with content changes being made in the other main memory to cause the first and second main memories to continue having the same contents; and

means for automatically changing system operation from a first to a second mode of operation transparently to execution of application tasks in response to certain conditions, wherein in the first mode both processors are active and each is executing substantially independently of the other tasks selected from a different one of a first and a second group of tasks, and wherein in the second mode of operation a selected either one of the processors is inactive and the other of the processors is active and executing tasks selected from both the first and second groups of tasks, the operation-changing means including means for fully occupying processor state of the one processor with at least one task that need not be continued on the other processor, at time of inactivation of the one processor, to ensure that any processor state existent in the one processor during the first mode of operation prior to the inactivation and relating to an application task not completed by the one processor is stored by the one processor in the one processor'"'"'s main memory and by operation of the memory updating means is copied form the one processor'"'"'s main memory to the other processor'"'"'s main memory to be available to the other processor for execution of the related application task during the second mode of operation without recalculation by the other processor of the processor of the processor state relating to the application task.

2. The system of claim 1 wherein the certain conditions comprise manual and program commands and system fault conditions.

3. The system of claim 1 wherein

the means for occupying processor state comprise

an uniterruptible task for stopping the one processor to end the first mode of operation, and for assigning the first and second groups of tasks for execution to the active other processor to begin the second mode of operation,

a task having lowest-priority in the one processor, when executed for effecting execution of the uninterruptible task, the execution of the lowest-priority task ensuring absence of interrupted tasks from the one processor and thereby ensuring presence in the main memory of any processor state of the one processor relating to an application task not completed by the one processor, and

means responsive to the certain conditions for scheduling for execution the lowest-priority task to initiate the changing of system operation from the first mode to the second mode.

4. The system of claim 3 further comprising a first dispatch queue stored in the main memories and associated with the other processor for identifying tasks of the first group during the first mode of operation and for identifying tasks of the first and the second group during the second mode of operation, and further comprising a second dispatch queue stored in the main memories and associated with the one processor for identifying tasks of the second group during the first mode of operation;

and wherein

the uninterruptible task is for stopping the one processor and causing the other processor to converge the first and second dispatch queues to the first dispatch queue to begin the second mode of operation.

5. The system of claim 1 further comprising:

first and second peripheral means;

first controller means interposed between the first peripheral means and the first and the second processors for selectively connecting the first peripheral means with one of the first and the second processors to give either processor, when active, access to the first peripheral means for purposes of execution of tasks on that processor; and

second controller means interposed between the second peripheral means and the first and the second processors for selectively connecting the second peripheral means with one of the first and the second processors to give either processor, when active, access to the second peripheral means for purposes of execution of tasks on that processor.

6. A processing system comprising:

a first and a second processor;

a first main memory included in the first processor and a second main memory included in the second processor, the first and second main memories duplicating each other'"'"'s contents;

means interconnecting the first and the second main memories, when active for automatically updating each main memory with content changes being made in the other main memory to cause the first and second main memories to continue having the same contents; and

means for automatically changing system operation from a first to a second mode of operation transparently to execution of application tasks in response to certain conditions, wherein in the second mode both processors are active and each is executing substantially independently of the other tasks selected from a different one of a first and a second group of tasks, and wherein in the first mode one of the processors is inactive and the other of the processors is active and executing tasks selected from both the first and the second group of tasks, the operation-changing means including means for causing the active other processor during the first mode of operation to change contents of the memory of the active other processor, thereby to effect like changes of contents of the memory of the one processor by way of the memory updating means copying the changed contents of the memory of the active other processor into the memory of the one processor, in order to prepare the one processor for becoming activated and to assign one of the groups of tasks to the one processor for execution during the second mode of operation, and further for causing the active other processor to activate the one processor in order to begin the second mode of operation.

7. The system of claim 6 wherein the certain conditions comprise manual and program commands and system fault conditions.

8. The system of claim 6 wherein

the means for causing comprise

a task executed by the active other processor in response to the certain conditions to initiate change of system operation from the first to the second mode and including (a) task means for initializing an operating system of the one processor in the memory of the active other processor to cause like initialization to occur in the memory of the one processor by way of operation of the memory updating means, (b) task means for causing the one processor to execute maintenance tasks to ensure that the one processor may be entrusted with execution of application tasks in the second mode of operation, (c) task means for assigning one of the first and second groups of tasks for execution to the one processor in the memory of the active other processor to cause like assignment to occur in the memory of the one processor by way of operation of the memory updating means, and (d) task means for starting the one processor to begin the second mode of operation wherein the one processor executes tasks from the assigned one of the first and second groups of tasks.

9. The system of claim 8 further comprising

a first dispatch queue stored in the main memories and associated with the active other processor for identifying tasks of the first group during the second mode of operation and for identifying tasks of the first and the second group during the first mode of operation;

and the system further selectively comprising

a second dispatch queue stored in the main memories and associated with the one processor for identifying tasks of the second group during the second mode of operation;

wherein

the task means for initializing comprise

means for initializing the second dispatch queue; and

wherein

the task means for assigning comprise

means for diverging the second group of tasks to the second dispatch queue from the first dispatch queue.

10. The system of claim 6 further comprising:

first and second peripheral means;

first controller means interposed between the first peripheral means and the first and the second processors for selectively connecting the first peripheral means with one of the first and the second processors to give either processor, when active, access to the first peripheral means for purposes of execution of tasks on that processor; and

second controller means interposed between the second peripheral means and the first and the second processors for selectively connecting the second peripheral means with one of the first and the second processors to give either processor, when active, access to the second peripheral means for purposes of execution of tasks on that processor.

11. A processing system comprising;

as first and a second processor;

a first main memory included in the first processor and a second main memory included in the second processor, the first and second main memories duplicating each other'"'"'s contents; and

means interconnecting the first and the second main memories, when active for automatically updating each main memory with content changes being made in the other main memory to cause the first and second main memories to continue having the same contents; and

means cooperative with the memory updating means for automatically changing processor operation from any one to another of a first, a second, and a third mode of operation in response to certain conditions, the changes from one to another of the first and the second modes being transparent to execution of application tasks, wherein in the first mode both processors are active and each is executing substantially independently of the other programs selected from a different one of a first and a second group of tasks, wherein in the second mode one of the processors is active and executing tasks of both groups and the other of the processors is standing by ready to assume execution of tasks and wherein in the third mode one of the processors is active and executing tasks of both groups and the other of the processors is unavailable to assume execution of tasks.

12. The system of claim 11 wherein the certain conditions comprise manual and program commands and a soft and a hard type of system fault conditions.

13. The system of claim 11 wherein the means for automatically changing system operation comprise:

means for selectively starting and stopping a selected processor to effect change of operation from one to another of the modes;

means for selectively identifying a stopped processor as being out of service during the third mode of operation; and

means cooperative with the starting and stopping means and with the memory updating means for assigning both the first and second groups of task for execution to the active processor when one processor is stopped during the second and the third modes of operation, and for assigning the first group of tasks to the primary processor and the second group of tasks to the secondary processor when both processors are active during the first mode of operation, the assigning means performing the assignment in the memory of one processor thereby to effect like assignment in the memory of the other processor by way of operation of the memory updating means.

14. The system of claim 13 further comprising

a first dispatch queue stored in the main memories and associated with the primary processor for identifying tasks of the first group during the first mode of operation, and for identifying tasks of the first and the second group during the second and third modes of operation;

and the system further selectively comprising

a second dispatch queue stored in the main memories and associated with the secondary processor for identifying tasks of the second group during the first mode of operation; and

wherein

the assigning means comprise

means for converging the first and second dispatch queues to the first dispatch queue when one processor is stopped during exit from the first mode of operation, and

means for diverging the first an second queues from the first dispatch queue when both processors become active during entry into the first mode of operation.

15. The system of claim 11 further comprising:

first and second peripheral means;

first controller means interposed between the first peripheral means and the first and the second processors for selectively connecting the first peripheral means with one of the first and the second processors to give either processor, when active, access to the first peripheral means for purposes of execution of task on that processor; and

second controller means interposed between the second peripheral means and the first and the second processors for selectively connecting the second peripheral means with one of the first and the second processors to give either processor, when active, access to the second peripheral means for purposes of execution of tasks on that processor.

19. The system of claim 11 wherein the operation-changing means comprise:

means for automatically changing processor operation from one to another of six states of operation in response to certain conditions, wherein in the first and second states both processors are active and each is executing substantially independently of the other programs selected from a different one of a first and a second group of tasks such that in the first state the first processor is designated the primary processor, for executing tasks of the first group, and the second processor is designated the secondary processor, for executing tasks of the second group, and such that in the second state the second processor is designated the primary processor, for executing tasks of the first group, and the first processor is designated the secondary processor, for executing tasks of the second group, wherein in the third and fourth states one of the processors is active and executing tasks of both groups and the other of the processors is standing by ready to assume execution of tasks such that in the third state the first processor is active and such that in the fourth state the second processor is active, the changes from one to another of the first, second, third, and fourth states being transparent to execution of application tasks, and wherein in the fifth and sixth states one of the processors is active and executing tasks of both groups and the other of the processors is unavailable to assume execution of tasks such that in the fifth state the first processor is active and such that in the sixth state the second processor is active.

16. In a processing system that includes a first and a second processor, a first main memory included in the first processor and a second main memory included in the second processor, the first and second main memories having the same contents including programs that include fault recovery programs and a first dispatch queue for holding identities of programs designated for execution, and apparatus interconnecting the first and second memories for automatically updating each main memory with content changes being made in the other main memory, a method of automatically changing system operation transparently to execution of application programs from a first state wherein the second processor is inactive and the first processor is active and executing programs selected from those indentified by the first dispatch queue to a second state wherein there are in each main memory the first and a second dispatch queue each for holding identities of programs designated for execution by a different one of the first and second processor, and wherein both processors are active an executing substantially independently of each other programs identified by their respective dispatch queues, the method comprising the step of:

creating the second dispatch queue for identifying programs designated for execution by the second processor during the second mode of operation, in the main memory of the first processor thereby to effect like creation in the main memory of the second dispatch queue from the main memory of the first processor to the main memory of the second processor;

creating shadow fault recovery programs comprising selected portions of the fault recovery programs for performing on the second processor fault recovery activities performable on a per-processor basis;

setting the second processor to a known state to initialize the second processor;

placing the identity of the shadow fault recovery programs in the second dispatch queue in the main memory of the first processor thereby to effect like placing in the main memory of the second processor by operation of the memory updating means;

executing the shadow fault recovery programs on the second processor to ensure that the second processor may be entrusted with execution of application tasks in the second mode of operation;

transferring the identity of programs, designated for execution by the second processor during the second mode of operation from the first to the second dispatch queue in the main memory of the first processor thereby to effect like transfer in the main memory of the second processor by operation of the memory updating means;

starting the second processor to execute programs identified by the second dispatch queue to commence the second mode of operation; and

continuing execution by the first processor of programs identified by the first dispatch queue.

17. In a processing system that includes a first and a second processor, an indicator arrangement for designating selectively either one of the processors as a primary processor and designating the other processor as a secondary processor, a first main memory included in the first processor and a second main memory included in the second processor, the first and second main memories having the same contents including programs that include the first and second main memories having the same contents including programs that include a first an a second program, fault recovery programs, and shadow fault recover programs comprising selected portions of the fault recover programs, and a first and a second dispatch queue for holding the identities of programs designated for execution by the primary and secondary processor, respectively, and apparatus interconnecting the first and second main memories for automatically updating each main memory with content changes being made in the other main memory, a method of automatically changing system operation transparently to execution of application programs from a first state wherein both processors are active and executing substantially independently of each other programs identified by their respective dispatch queues to a second state wherein the second processor is standing by ready to assume execution of programs and the first processor is active and executing programs selected from programs identified by the first dispatch queue, the method comprising the steps of:

placing the identity of the first program in the dispatch queue of the second processor to initiate a change of system operation from the first to the second mode;

commencing to execute the first program only when no interrupted programs are identified by the dispatch queue of the second processor to ensure that any processor state existent in the second processor during the first mode of operation and relating to an application task not completed by the second processor is stored by the second processor in the second processor'"'"'s main memory and by operation of the memory updating means is copied from the second processor'"'"'s main memory to the first processor'"'"'s main memory to be available to the first processor for execution of the related application task during the second mode of operation;

causing the second program to be executed on the second processor, in response to execution of the first program, the second program being executed without interruption to ensure that a processor state relating to an application task is not formed by the second processor during system transition between the first and second modes of operation;

interrupting the first processor in response to execution of the second program to cause the first processor to complete the system transition from the first to the second mode of operation;

stopping the second processor;

moving identity of programs from the second dispatch queue to the first dispatch queue to designate for execution by the primary processor during the second mode of operation programs designated for execution by the secondary processor during the first mode of operation, in response to the interruption;

removing the identity of shadow fault recovery programs from the first dispatch queue to avoid during subsequent program execution duplication of activities of the fault recovery programs;

checking the indicator arrangement to determine whether the first processor is designated the primary processor;

changing the indicator arrangement to switch the processors designations if the first processor is not designated the primary processor, to cause the first processor to select for execution programs from the first dispatch queue during the second mode of operation; and

continuing to execute on the first processor programs identified by the first dispatch queue, in the second mode of operation.

18. In a processing system that includes a first and a second processor, an indicator arrangement for designating selectively either one of the processors as a primary processor and designating the other processor as a secondary processor, a first main memory included in the first processor and a second main memory included in the second processor, the first and second main memories having the same contents including programs that include fault recovery programs and shadow fault recovery programs comprising selected portions of the fault recovery programs, and a first and a second dispatch queue for holding the identities of programs designated for execution by the primary and secondary processor, respectively, and apparatus interconnecting the first and second main memories when active for automatically updating each main memory with content changes being made in the other main memory, a method of automatically changing system operation from a first state wherein both processors are active and executing substantially independently of each other programs identified by their respective dispatch queues to a second state wherein the second processor is out of service and the first processor is active and executing programs selected from programs identified by the first dispatch queue, the method comprising the steps of:

stopping the second processor to terminate the first mode of operation;

deactivating the main memory updating apparatus to cease updating of the main memory of the second processor with changes to the contents of the main memory of the first processor;

moving the identities of programs from the second to the first dispatch queue to designate for execution by the primary processor during the second mode of operation programs designated for execution by the secondary processor during the first mode of operation;

initializing the processes identified by the first dispatch queue to effect recovery of the processes from any events that lead to termination of the first mode of operation;

removing identities of the shadow fault recovery programs from the first dispatch queue to avoid during subsequent program execution duplication of activities of the fault recovery programs;

checking the indicator arrangement to determine whether the first processor is designated the primary processor;

changing the indicator arrangement to switch the processors'"'"' designations if the first processor is not designated the primary processor to cause the first processor to select for execution programs from the first dispatch queue during the second mode of operation; and

continuing to execute on the first processor programs identified by the first dispatch queue, in the second mode of operation.