Computer-aided automatic wiring method for semiconductor integrated circuit device

• US 4,823,276 A
• Filed: 03/16/1987
• Issued: 04/18/1989
• Est. Priority Date: 03/20/1986
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hiwatashi, Tamotsu
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): TRANS, VINCENT N
• Application Number:
  US07/026,301
• Time in Patent Office: 764 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/300
• US Class Current: 716/128
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A computer-aided automatic wiring method is disclosed, which determines a wiring pattern for a semiconductor IC device in which function blocks are arranged on a substrate and channel are defined around the blocks to serve as wiring regions. First, electrical connecting paths between associated blocks at one channel (a first channel) are determined to obtain a normal wiring pattern in accordance with a bonding request. Subsequently, if another channel (a second channel) already subjected to normal wiring is present among channels adjacent to the first channel, these channels are merged before the next channel is subjected to normal wiring so as to define a new expanded channel (a third channel). A combined wiring pattern of the third channel, obtained simply by combining wiring patterns of the first and second channels, is then modified conform to the shortest routing rule. If a vacant space is found in the modified wiring pattern, the space is removed to reduce the size of the third channel. The processing is repeatedly executed with respect to every channel, thereby optimizing the entire wiring pattern of the IC device to maximize its packing density.

Claims

1. An automatic wiring method for a semiconductor integrated circuit device in which function blocks selected to obtain desired logical functions are arranged on a substrate and channels are defined around the function blocks to serve as wiring regions, said method comprising the steps of:

(a) selecting a first channel from the channels on said substrate in accordance with a predetermined processing order;

(b) performing routing/wiring processing to determine electrical connecting paths between associated function blocks in said first channel in accordance with a bonding request, thereby obtaining a normal wiring pattern;

(c) detecting, after the routing/wiring processing is completed, a second channel which neighbors said first channel and has been already subjected to normal routing/wiring processing, said second channel having a processing order immediately before a processing order of said first channel;

(d) merging said first and second channels to form a new third channel, the area of which is expanded, said third channel having a combined wiring pattern obtained by combining wiring patterns of said first and second channels;

(e) performing wiring pattern rearranging to modify said combined wiring pattern of said third channel to matching with the shortest routing rule at an expanded space of said third channel; and

(f) verifying whether a vacant space not contributing to wiring is left in the modified wiring pattern of said third channel, and if such a vacant space is detected, removing the vacant space to reduce the area of said third channel, thereby to optimize the entire wiring pattern of said integrated circuit device and maximize packing density of said integrated circuit device.

2. The method according to claim 1, further comprising:

(g) detecting, after the rearranging process is completed, a fourth channel which neighbors said third channel and has been already subjected to normal routing/wiring processing;

(h) merging said third and fourth channels to form a new fifth channel, the area of which is further expanded, said fifth channel having a combined wiring pattern obtained by combining wiring patterns of said third and fourth channels;

(i) performing wiring pattern rearranging to modify said combined wiring pattern of said fifth channel to match with the shortest routing rule at an expanded space of said fifth channel; and

(j) verifying whether a vacant space not contributing to wiring is left in the modified wiring pattern of said fifth channel, and if such a vacant space is detected, removing the vacant space to reduce the area of said fifth channel.

3. The method according to claim 1, wherein said channels including said first and second channels extend along first and second directions perpendicular to each other on said substrate and are substantially defined by boundaries on which wiring is prohibited to be formed, and wherein the corresponding boundary or boundaries are removed from said combined wiring pattern of said third channel, thereby increasing spaces at the third channel where wires are allowed to extend.

4. The method according to claim 3, wherein each of said channels including said first and second channels has tracks defined along at least one of said first and second directions, and the number of said tracks corresponds to the number of wires allowed to extend therein.

5. The method according to claim 4, wherein, when said corresponding boundary or boundaries which separate said first and second channels are removed from said combined wiring pattern of said third channel newly defined by merging said first and second channels, a space of said third channel left at the position where said boundary is removed is allowed to serve as a new track.

6. The method according to claim 5, wherein said normal wiring processing executed to said first channel corresponds to local wiring optimization processing, and said pattern modification processing executed to said combined wiring pattern of said third channel corresponds to total wiring optimization processing.

7. The method according to claim 5, wherein said normal wiring processing and said pattern modification processing are repeatedly applied to channels sequentially specified in accordance with said processing order, so that when the pattern modification processing is executed at the last channel, modification has been performed to optimize the wiring pattern of the entire region of said substrate.

8. The method according to claim 7, wherein said function blocks are selected to include at least one of a memory unit and a calculation unit.

9. The method according to claim 8, wherein said memory unit is selected to include at least one of a random access memory and a read only memory.

10. The method according to claim 9, wherein said calculation unit is selected to include at least one of a programmable logic array, an arithmetic logic unit, and a central processing unit.

11. The method according to claim 7, wherein said function blocks comprise a polycell.