Graphic display apparatus having boundary detection target region designating circuit

• US 4,823,282 A
• Filed: 09/24/1986
• Issued: 04/18/1989
• Est. Priority Date: 09/27/1985
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamagami, Nobuhiko
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/911,060
• Time in Patent Office: 937 Days
• Field of Search: 364/518, 364/523, 340/724, 340/734, 340/747
• US Class Current: 345/620
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A boundary detection target region designating circuit includes a maximum value register in which a predetermined minimum value is initially set, and a minimum value register in which a predetermined maximum value is initially set. The content of the maximum value register is compared with a vertex coordinate of a boundary written in a boundary detection memory by a first comparator. If it is detected that the vertex coordinate is larger than the content of the maximum value register, the content of the maximum value register is updated to be the vertex coordinate by a first updating means. The content of the minimum value register is compared with the vertex coordinate by a second comparator. If it is detected that the vertex coordinate is smaller than the content of the minimum value register, the content of the minimum value register is updated to be the vertex coordinate by a second updating means. After a boundary write operation into the boundary detection memory is completed, maximum and minimum coordinates of a minimum rectangular region including all the boundaries of blanked-out regions are indicated by the maximum and minimum value registers.

Claims