Serial data direct memory access system

• US 4,823,305 A
• Filed: 05/26/1988
• Issued: 04/18/1989
• Est. Priority Date: 07/18/1986
• Status: Expired due to Fees

• Current Assignee: Chrysler Motors Corporation Highland Park MI
• Original Assignee: Chrysler Motors Corp (Stellantis NV)
• Inventors: Holdren, Earl J., Owski, Alexander J.
• Primary Examiner(s): Heckler, Thomas M.
• Assistant Examiner(s): KULIK, PAUL V
• Application Number:
  US07/203,620
• Time in Patent Office: 327 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 370/1, 360/5
• US Class Current: 710/30
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A serial data direct memory access system including a control circuit that shares control with a master computer of an interface bus of a DMA storage system. Serial data is supply to the control circuit via a fiber optic cable. The control circuit employs means responsive to status code bits of the message words for gaining control from the master computer of the interface bus and for directly accessing the computer controlled bus memory storage system. This system is capable of handling data streams of infinite lengths. Also, means are provided for preventing bit errors from interfering with critical message words.

Claims

1. A method for storing transient response data derived from rapidly changing physical phenomena, said data being in the form of serial digital numbers, said method includes the steps of:

(a) adding a predetermined number of code bits to each of said digital numbers to form a digital word having a START bit, a select number of operational bits and a frame of information bits, said digital word providing a particular protocol for processing transient response data;

(b) adding a clock signal of a chosen frequency to each of said data words;

(c) encoding each of said serial words and said added clock signal into a chosen code format suitable for data transmission;

(d) transmitting each of said encoded serial words and clock signal as digital light signal stream over a fiber optic cable to an optical receiver, said optical receiver being capable of receiving the light signal stream transmitted over said optical fiber cable;

(e) at said digital receiver, converting said digital light signal stream transmitted over said fiber optics cable into a reconstructed encoded serial digital electric signal data stream;

(f) decoding said serial digital electric signal data stream so as to reconstruct each of said serial digital data words and said added clock signal;

(g) counting each bit in each of said serially presented word to detect said START bit to provide an indicating of a sufficient number of bits for forming a message word;

(h) sequentially shifting each bit of said serial digital electric signal data onto parallel output lines at the reconstructed added clock rate;

(i) latching at said parallel output lines the sufficient number of serial bits of said data stream in response to the indication of the START bit to reconstruct each of said data words which form a messge word;

(j) providing a direct memory access computer bus system comprised of a master computer, an interface bus, and static and dynamic memories;

(k) providing a control circuit capable of sharing control of said interface bus with said master computer, said control circuit being responsive to each of said message words in controlling directly accessing said memories of said bus system;

(l) providing a message word used in conjunction with subsequent critical message words needed for operating said control circuits for preventing erroneous messages being employed to operate said control circuit;

(m) providing a critical message word used to operate said control circuit so as to arbitrate with said master computer for control over said interface bus;

(n) decoding each of said operational code bits of each word so as to operate said control circuit in either a pre-DMA mode, a DMA mode or a post DMA mode;

(o) after gaining control over said interface bus, forming an address word which is added to each of said data words for providing an address location in the memories of said computer memory system for each of said message words that is stored in memory.

(p) designating block locations of memory for storing designated forms of message words;

(q) writing a plurality of sample data words into memory address and block locations corresponding to the locations designated by each of said formed address words and the designated blocks, the writing of said sample data words being such as to exhort the memory locations causing over writing of the data in memory locations specified to receive the sample data;

(r) writing the transient response data in memory in a manner preventing the overwrite of such data; and

(s) after said control circuit finishes controlling accessing the memories via said interface bus, relinquishing control of said interface bus to said master computer.

2. The method of claim 1 which includes rolling said sample data message words in and out of said memories in a loop.

3. The method of claim 1 which including distinguishing faults in said control circuit from faults in the device transmitting said message words to said control circuits.

4. A system for storing transient response data derived from rapidly changing physical phenomena, said data being in the form of serial digital numbers, said system comprises:

(a) means for adding a predetermined number of code bits to each of said digital numbers to form a digital word having a START bit, a select number of operational bits and a frame of information bits, said digital word providing a particular protocol for processing transient response data;

(b) means for adding a clock signal of a chosen frequency to each of said data words;

(c) means for encoding each of said serial words and said added clock signal into a chosen code format suitable for data transmission;

(d) means for transmitting each of said encoded serial words and clock signal as digital light signal stream over a fiber optic cable to an optical receiver, said optical receiver being capable of receiving the light signal stream transmitted over said optical fiber cable;

(e) at said digital receiver, means for converting said digital light signal stream transmitted over said fiber optics cable into a reconstructed encoded serial digital electric signal data stream;

(f) means for decoding said serial digital electric signal data stream so as to reconstruct each of said serial digital data words and said added clock signal;

(g) means for counting each bit in each of said serially presented word to detect said START bit to provide an indicating of a sufficient number of bits for forming a message word;

(h) means for sequentially shifting each bit of said serial digital electric signal data onto parallel output lines at the reconstructed added clock rate;

(i) means for latching at said parallel output lines the sufficient number of serial bits of said data stream in response to the indication of the START bit to reconstruct each of said data words which form a message word;

(j) means for providing a direct memory access computer bus system comprised of a master computer, an interface bus, and static and dynamic memories;

(k) means for providing a control circuit capable of sharing control of said interface bus with said master computer, said control circuit being responsive to each of said message words in controlling directly accessing said memories of said bus system;

(l) means for providing a message word used in conjunction with subsequent critical message words needed for operating said control circuits for preventing erroneous messages being employed to operate said control circuit;

(m) means for providing a critical message word used to operate said control circuit so as to arbitrate with said master computer for control over said interface bus;

(n) means for decoding each of said operational code bits of each word so as to operate said control circuit in either a preDMA mode, a DMA mode or a post DMA mode;

(o) after gaining control over said interface bus, means for forming an address word which is added to each of said data words for providing an address location in the memories of said computer memory system for each of said message words that is stored in memory;

(p) means for designating block locations of memory for storing designated forms of message words;

(q) means for writing a plurality of sample data words into memory address and block locations corresponding to the locations designated by each of said formed address words and the designated blocks, the writing of said sample data words being such as to exhort the memory locations causing over writing of the data in memory locations specified to receive the sample data;

(r) means for writing the transient response data in memory in a manner preventing the overwrite of such data; and

(s) after said control circuit finishes controlling accessing the memories via said interface bus, means for relinquishing control of said interface bus to said master computer.

5. The system of claim 4 which includes means for rolling said sample data message words in and out of said memories in a loop.

6. The system of claim 4 which includes means for distinguishing faults in said control circuit from faults in the device transmitting said message words to said control circuits.