Method of making DRAM cell with trench capacitor
First Claim
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1. A method for forming a coupled capacitor and transistor comprising the steps of:
- forming a trench in the surface of a substrate;
coating the surfaces of said trench with a first insulating layer;
forming a first conductive region by filling the remainder of said trench with a conductive material;
etching back said insulating layer and said conductor material to a level within said trench;
forming a second conductive region by depositing conductive material in the portion of said trench opened by a said etching step;
etching back said second conductive region to a level within said trench but above said insulating layer;
forming a source region in said substrate, said source region electrically connected to said second conductive region;
forming a second insulating layer on the exposed surfaces of said trench and on the exposed surface of said second conductive material;
forming drain regions adjacent to the intersection between said trench and the surface of said substrate;
forming a third conductive region by filling the remaining portion of said trench with a conductive material, said third conductive region serving as a gate controlling current between said source and said drain.
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Abstract
A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel, and drain and one capacitor plate are formed essentially vertically in the sidewalls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench. Signal charge is stored on the material inserted into the trench. In preferred embodiments word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface are formed as diffusions in the substrate which also form the drains. The trenches and cells are formed at the crossings of bit lines and word lines; the bit lines and the word lines form perpendicular sets of parallel lines.
152 Citations
46 Claims
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1. A method for forming a coupled capacitor and transistor comprising the steps of:
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forming a trench in the surface of a substrate; coating the surfaces of said trench with a first insulating layer; forming a first conductive region by filling the remainder of said trench with a conductive material; etching back said insulating layer and said conductor material to a level within said trench; forming a second conductive region by depositing conductive material in the portion of said trench opened by a said etching step; etching back said second conductive region to a level within said trench but above said insulating layer; forming a source region in said substrate, said source region electrically connected to said second conductive region; forming a second insulating layer on the exposed surfaces of said trench and on the exposed surface of said second conductive material; forming drain regions adjacent to the intersection between said trench and the surface of said substrate; forming a third conductive region by filling the remaining portion of said trench with a conductive material, said third conductive region serving as a gate controlling current between said source and said drain. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming a contact on a wall extending into a substrate substantially perpendicular to the surface of said substrate comprising the steps of:
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(a) forming an insulating layer on said wall; (b) forming a conductor including part of a device along at least a portion of said wall; (c) removing said conductor from along a part of said wall; (d) removing a portion of said insulating layer; and (e) forming a contact to said wall within at least a part of said portion of said insulating layer utilizing a conductive material in contact with said conductor. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A method of forming a contact on a wall extending into a substrate at an angle to the surface of said substrate comprising the steps of:
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(a) forming an insulating layer on said wall; (b) forming a conductor including part of a device along at least a portion of said wall; (c) removing said conductor from along a part of said wall; (d) removing a portion of said insulating layer; and (e) forming a contact to said wall within at least a part of said portion of said insulating layer utilizing a conductive material in contact with said conductor. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
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Current AssigneeTexas Instruments, Inc.
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Original AssigneeTexas Instruments, Inc.
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InventorsRichardson, William F., Malhi, Satwinder S.
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Primary Examiner(s)Hearn, Brian E.
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Assistant Examiner(s)Thomas, Tom
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Application NumberUS07/122,559Time in Patent Office530 DaysField of Search437/203, 437/47, 437/60, 437/919, 437/38, 437/48, 437/203, 437/52, 437/162, 437/249, 357/23.6US Class Current438/246CPC Class CodesH01L 29/66181 Conductor-insulator-semicon...H10B 12/0383 wherein the transistor is v...
