Trench isolation process and structure

• US 4,825,277 A
• Filed: 11/17/1987
• Issued: 04/25/1989
• Est. Priority Date: 11/17/1987
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Fong, Steven, Mattox, Robert
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US07/122,086
• Time in Patent Office: 525 Days
• Field of Search: 357/49.54, 357/55
• US Class Current: 257/639
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264

Abstract

A structure and method for forming an isolation wall in an etched trench are described. The trench walls are covered by a thin silicon oxide layer and the trench conformally filled with an oxy-nitride mixture having a particular range of composition so as to produce a neutral to slight tensile stress in the oxy-nitride relative to silicon. The structure is very simple to fabricate and creates fewer defects in the silicon substrate than prior art techniques. Buried voids in the filled trench are eliminated.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a major surface;

a trench extending into said substrate from said major surface wherein said trench has a sidewall and a bottom;

a silicon oxide-silicon nitride mixture substantially filling said trench to a first surface below said major surface; and

a silicon nitride layer completely covering said mixture.

2. The device of claim 1 wherein said substrate comprises a semiconductor body having a surface dielectric layer thereon extending to said major surface and wherein said trench extends into said body and further comprising a silicon oxide lining covering at least said sidewall of said trench.

3. The device of claim 1 further comprising a silicon nitride filled region centrally located in said mixture.

4. The device of claim 1 wherein said silicon oxide-silicon nitride mixture comprises a silicon oxy-nitride having an equivalent mole fraction of silicon nitride in the range 0.1-0.5 silicon nitride.

5. The device of claim 4 wherein said equivalent mole fraction of silicon nitride is in the range 0.1-0.4 silicon nitride.

6. The device of claim 5 wherein said equivalent mole fraction of silicon nitride is in the range 0.1-0.3 silicon nitride.

7. The device of claim 6 wherein said equivalent mole fraction of silicon nitride is in the range 0.1-0.20 silicon nitride.

8. The device of claim 1 wherein said silicon oxide-silicon nitride mixture exhibits tensile stress relative to silicon.

9. The device of claim 8 wherein said tensile stress is less than 5×

10⁹ dynes/cm².

10. The device of claim 1 wherein said silicon oxide-silicon nitride mixture has a refractive index in the range about 1.5-1.8.

11. A semiconductor device comprising:

a substrate comprising a semiconductor body;

a trench extending into said body;

a silicon oxy-nitride mixture in said trench; and

a silicon nitride layer completely covering said silicon oxy-nitride mixture in said trench.