Digital video signal processor

• US 4,825,287 A
• Filed: 06/18/1987
• Issued: 04/25/1989
• Est. Priority Date: 06/20/1986
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Matsuura, Tatsuji, Baji, Toru, Tsukada, Toshiro, Ohba, Shinya
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Parker, Michael D.
• Application Number:
  US07/063,476
• Time in Patent Office: 677 Days
• Field of Search: 358/160, 358/22, 358/11, 358/12, 358/140, 358/141, 358/183, 358/105
• US Class Current: 348/720
• CPC Class Codes: H04N 5/14 Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00

Abstract

According to the present invention, the number of elements of a signal processing circuit or the like can be drastically reduced by conducting a time-multiplex processing. In a transversal filter having a coefficient of symmetry of 16 taps, for example, the prior art requires about 58,000 transistors. In case four signal processing cores (i.e., SPC) having a function of four taps are used, the number of transistors required can be reduced to about 34,000 by a duplexing process. In case two SPCs having a function of eight taps are used, the number can be reduced to about 19,000 by a quadplexing process. In case, moreover, one SPC having a function of sixteen taps is used, the number can be reduced to about 13,000 by an octaplexing process. Here, the reason why the number of elements is not halved even if the number of the SPCs is halved is that the number of elements to be used in control circuits, memories and so on increases.

Claims

1. A digital video signal processor comprising:

(1) a first signal processing core for processing a plurality of digital video signals, said first signal processing core having an M_A1 number of arithmetic logic units and an M_M1 number of multipliers; and

(2) a second signal processing core having its input responding to an output of said first signal processing core for filtering said output of said first signal processing core, said second signal processing core having an M_A2 number of arithmetic logic units and an M_M2 number of multipliers,

wherein, a sampling time shared between said first and second signal processing cores is designated as T;

processing times of said arithmetic logic units of said first and second signal processing cores are designated as τ

_A1 and τ

_A2, respectively;

processing times of said multipliers of said first and second signal processing cores are designated as τ

_M1 and τ

_M2, respectively;

a number of program steps of said first and second signal processing cores are designated as P₁ and P₂, respectively;

a number of additions and subtractions of said first and second signal processing cores are designated as N_A1 and N_A2, respectively; and

a number of multiplications of said first and second signal processing cores are designated as N_M1 and N_M2, respectively, and wherein said digital video signal processor is time-multiplexed by using numbers M_A1 and M_M2 of said arithmetic logic units and said multipliers respectively, wherein the following relations are satisfied

space="preserve" listing-type="equation">N.sub.Ai ≦

P.sub.i ·

M.sub.Ai ;

space="preserve" listing-type="equation">and

space="preserve" listing-type="equation">N.sub.Mi ≦

P.sub.i ·

M.sub.Mi (i=1,

     2); and

space="preserve" listing-type="equation">at program step P.sub.i the following relations are satisfied

space="preserve" listing-type="equation">τ

.sub.i =max(τ

.sub.Ai, τ

.sub.Mi);

space="preserve" listing-type="equation">and

space="preserve" listing-type="equation">T/τ

.sub.i ≧

P.sub.i (i=1,

     2).

2. A digital video signal processor as defined in claim 1,

wherein said each of said signal processing cores has a phase locked loop for generating a reference signal for instruction execution.

3. A digital video signal processor as defined in claim 2,

wherein said second signal processing core has delay circuits each for delaying an input signal, a circuit for latching an external signal directly in said arithmetic logic units, a circuit for extracting the outputs of said arithmetic logic units directly to the outside, and means for setting the number of frequency divisions of a counter in said phase locked loop.

4. A digital video signal processor as defined in claim 1,

wherein said second signal processing core has its delay circuits enabled to have the delay times set independently of one another.