Video translation system for translating a binary coded data signal into a video signal and vice-versa

• US 4,825,306 A
• Filed: 03/10/1987
• Issued: 04/25/1989
• Est. Priority Date: 08/08/1983
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Robers, Klaas H. J.
• Primary Examiner(s): PSITOS, ARISTOTELIS
• Application Number:
  US07/024,902
• Time in Patent Office: 777 Days
• Field of Search: 360/8, 360/9.1, 360/32, 360/19.1, 360/32, 360/53, 360/54, 360/51, 371/69, 358/142, 358/145, 358/143
• US Class Current: 386/208
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0682 Tape device
• CPC Class Codes: G11B 20/12 Formatting, e.g. arrangement of data block or words on the record carriers within interface between computers and data recorders G06F3/06
• CPC Class Codes: G11B 20/18 Error detection or correction; Testing , e.g. of drop-outs

Abstract

The binary coded data signal is divided into data blocks in the video translation system in accordance with the invention. n copies are made of each data block. Televison synchronization signals are added to the original data block and to the n copies thereof, the assembly thus forming a video data block. This video data block is transferred to a video processing device, for example, a video recorder in which it is recorded. When the video data block is recovered, the corresponding data block is recovered from the n+1 data blocks present.

Claims

1. A video translation system comprising in combination

(a) a synchronization signal circuit generating television synchronization signals,

(b) a first device having a first connection terminal for receiving binary coded data signals from a data source and being provided for translating a received binary coded data signal into a video signal, said first device comprising

(i) a system of registers connected to said first connection terminal for receiving said binary coded data signals in the form of successive original data blocks and for storing temporarily each of said original data blocks, said system of registers having an input for receiving said television synchronization signals and comprising generating means for generating under control of associated television synchronization signals n copies of each of said original data blocks,

(ii) a mixer comprising a first input connected to said system of registers for receiving each original data block and its n copies, said mixer having a second input for receiving said associated television synchronization signals and forming for each original data block a data set having a predetermined number (n+1) of data blocks and associated television synchronization signals,

(iii) a video signal processing device connected to said mixer for receiving each of said data sets,

(c) a second device connected to said video signal processing device for translating each data set into a binary coded data signal, said second device comprising:

(i) a synchronization signal separating device for separating said associated television synchronization signals from each of said data sets received from said video signal processing device,

(ii) a shift pulse generator connected to said synchronization signal separating device for receiving said separated television synchronization signals of each video data set, said shift pulse generator generating in response to said separated television synchronization signals of each video data set a series of first shift pulses and for generating a second shift pulse each time n+1 series of first shift pulses are generated,

(iii) a recovery circuit including a majority circuit,

(iv) shifting means connected to said shift pulse generator and to an input of said recovery circuit, said shifting means having an input for receiving each said video set originating from said video signal processing device, said shifting means being provided for shifting into said recovery circuit under control of said first shift pulses the n+1 data blocks comprising each received video data set, and

(v) said recovery circuit receovering on the basis of a majority decision a corresponding binary coded data signal from each n+1 video data blocks in each received video data set and for outputting said corresponding binary coded data signal under control of a received second shift pulse.

2. A video translation system according to claim 1 wherein said recovery circuit includes a plurality of inputs equal in number to the predetermined number of data blocks in each data set.

3. A video translation system according to claim 2 wherein said shifting means includes a shift register connected to said majority decision circuit.

4. A video translation system according to claim 3 wherein said recovery circuit includes a further register connected to said majority decision circuit for storing recovered binary coded data signals said further register operating in response to said second shift pulses to output a recovered binary coded data signal.

5. A video translation system according to claim 1 wherein said synchronization signal circuit includes a television synchronization signal generator and a divider connected to said television synchronization signal generator, said divider generating first and second control signals and a control pulse in response to said television synchronization signals, and wherein said system of registers of said first device includes an input register connected to said divider, said input register receiving said original data blocks in response to said first control signals from said divider.

6. A video translation system according to claim 5 wherein said system of registers of said first device includes an end-around coupled register connected to said divider and said input register, said end-around coupled register receiving an original data block from said input register in response to said control pulse.

7. A video translation system according to claim 1 wherein said end-around coupled register is connected to said mixer and provides data blocks thereto in response to said second control signals, said end-around coupled register including a serial input for receiving data blocks provided to said mixer for generating said at least one copy of each said original data block.